Actually the R7 1700 is the chip that is priced the same or less than the 7700K. Overclocked to at least 3.9 ghz, it's basically almost the same as an 1800X. Not only does it close the gap in a lot of gaming tests, it "smokes" the 7700K in pure multi-threaded workloads, and is more than sufficient for gaming. Paul from Paul's hardware has an interesting video about the 1700 overclocking vs the 7700K. Conclusion is that if you want the MAXIMUM number of frames, still stick with the 7700K, but if you still want the multi-threaded performance and still have a good gaming experience, the 1700 is the way to go.
This actually sorta highlights a big flaw in AMD's line-up. Why bother spending $500 on the 1800X, when you can get the 1700 for $330 in addition to a cpu cooler, AND a good motherboard for the same price.
Agreed. If the 1800x had some headroom for OCing, it would not be a bad choice over the 1700. Hopefully we will see some improvements in headroom with bios, and MB revisions. Come to find out that it is a Windows issue as well, where Windows thinks the logical cores are physical cores.
Copied and pasted from ajc9988 @notebookreview
Well It turns out, its windows fault for the low performance!!!
Logical Processor to Cache Map:
*--------------- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
*--------------- Instruction Cache 0, Level 1, 64 KB, Assoc 4, LineSize 64
*--------------- Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64
*--------------- Unified Cache 1, Level 3, 16 MB, Assoc 16, LineSize 64
-*-------------- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
-*-------------- Instruction Cache 1, Level 1, 64 KB, Assoc 4, LineSize 64
-*-------------- Unified Cache 2, Level 2, 512 KB, Assoc 8, LineSize 64
-*-------------- Unified Cache 3, Level 3, 16 MB, Assoc 16, LineSize 64
--*------------- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
--*------------- Instruction Cache 2, Level 1, 64 KB, Assoc 4, LineSize 64
--*------------- Unified Cache 4, Level 2, 512 KB, Assoc 8, LineSize 64
--*------------- Unified Cache 5, Level 3, 16 MB, Assoc 16, LineSize 64
---*------------ Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
---*------------ Instruction Cache 3, Level 1, 64 KB, Assoc 4, LineSize 64
---*------------ Unified Cache 6, Level 2, 512 KB, Assoc 8, LineSize 64
---*------------ Unified Cache 7, Level 3, 16 MB, Assoc 16, LineSize 64
----*----------- Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
----*----------- Instruction Cache 4, Level 1, 64 KB, Assoc 4, LineSize 64
----*----------- Unified Cache 8, Level 2, 512 KB, Assoc 8, LineSize 64
----*----------- Unified Cache 9, Level 3, 16 MB, Assoc 16, LineSize 64
-----*---------- Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
-----*---------- Instruction Cache 5, Level 1, 64 KB, Assoc 4, LineSize 64
-----*---------- Unified Cache 10, Level 2, 512 KB, Assoc 8, LineSize 64
-----*---------- Unified Cache 11, Level 3, 16 MB, Assoc 16, LineSize 64
------*--------- Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------*--------- Instruction Cache 6, Level 1, 64 KB, Assoc 4, LineSize 64
------*--------- Unified Cache 12, Level 2, 512 KB, Assoc 8, LineSize 64
------*--------- Unified Cache 13, Level 3, 16 MB, Assoc 16, LineSize 64
-------*-------- Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
-------*-------- Instruction Cache 7, Level 1, 64 KB, Assoc 4, LineSize 64
-------*-------- Unified Cache 14, Level 2, 512 KB, Assoc 8, LineSize 64
-------*-------- Unified Cache 15, Level 3, 16 MB, Assoc 16, LineSize 64
--------*------- Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
--------*------- Instruction Cache 8, Level 1, 64 KB, Assoc 4, LineSize 64
--------*------- Unified Cache 16, Level 2, 512 KB, Assoc 8, LineSize 64
--------*------- Unified Cache 17, Level 3, 16 MB, Assoc 16, LineSize 64
---------*------ Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
---------*------ Instruction Cache 9, Level 1, 64 KB, Assoc 4, LineSize 64
---------*------ Unified Cache 18, Level 2, 512 KB, Assoc 8, LineSize 64
---------*------ Unified Cache 19, Level 3, 16 MB, Assoc 16, LineSize 64
----------*----- Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
----------*----- Instruction Cache 10, Level 1, 64 KB, Assoc 4, LineSize 64
----------*----- Unified Cache 20, Level 2, 512 KB, Assoc 8, LineSize 64
----------*----- Unified Cache 21, Level 3, 16 MB, Assoc 16, LineSize 64
-----------*---- Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
-----------*---- Instruction Cache 11, Level 1, 64 KB, Assoc 4, LineSize 64
-----------*---- Unified Cache 22, Level 2, 512 KB, Assoc 8, LineSize 64
-----------*---- Unified Cache 23, Level 3, 16 MB, Assoc 16, LineSize 64
------------*--- Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------*--- Instruction Cache 12, Level 1, 64 KB, Assoc 4, LineSize 64
------------*--- Unified Cache 24, Level 2, 512 KB, Assoc 8, LineSize 64
------------*--- Unified Cache 25, Level 3, 16 MB, Assoc 16, LineSize 64
-------------*-- Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
-------------*-- Instruction Cache 13, Level 1, 64 KB, Assoc 4, LineSize 64
-------------*-- Unified Cache 26, Level 2, 512 KB, Assoc 8, LineSize 64
-------------*-- Unified Cache 27, Level 3, 16 MB, Assoc 16, LineSize 64
--------------*- Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
--------------*- Instruction Cache 14, Level 1, 64 KB, Assoc 4, LineSize 64
--------------*- Unified Cache 28, Level 2, 512 KB, Assoc 8, LineSize 64
--------------*- Unified Cache 29, Level 3, 16 MB, Assoc 16, LineSize 64
---------------* Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
---------------* Instruction Cache 15, Level 1, 64 KB, Assoc 4, LineSize 64
---------------* Unified Cache 30, Level 2, 512 KB, Assoc 8, LineSize 64
---------------* Unified Cache 31, Level 3, 16 MB, Assoc 16, LineSize 64
each zen thread is being registered as an individual core with its own L2 and L3 cache. I.e. totaling 136 MB cache!!. this is using Windows Sysinternals. This explains the SMT troubles in the event that a thread bounced to a HT thinking its the real deal.
Compare VS Intel
Logical Processor to Cache Map:
**------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------ Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------ Unified Cache 0, Level 2, 256 KB, Assoc 4, LineSize 64
******** Unified Cache 1, Level 3, 6 MB, Assoc 12, LineSize 64
--**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**---- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**---- Unified Cache 2, Level 2, 256 KB, Assoc 4, LineSize 64
----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**-- Unified Cache 3, Level 2, 256 KB, Assoc 4, LineSize 64
------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------** Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------** Unified Cache 4, Level 2, 256 KB, Assoc 4, LineSize 64