dgower2 said:
Does the PCI Bus Run Independent of the FSB?
No, not independent. PCI is an Intel's Symmetric Processing (Time-Share/Time-Division Processing) design, the base architecture is that of a hub not a switch.
dgower2 said:
The question is: Does changing the FSB speed necessarily effect the PCI bus speed or are they mutually exclusive? Does it depend on the chipset? Please don't provide opinions; only respond if you know for sure.
It always does for ALL SYMMETRIC PROCESSING designs, they are inherently synchronous by default, "PCI Latency" is the optimized values for perfect symmetrical synchronous time slices. A classical compensation method for pseudo asynchronous independent bus operation is a huge cache per PCI/CPU/any? device, aleviating bus tied-up time-slice conflicts and priority contentions.
The first Joe User's hardware which could allow PCI bus independent and run asynchronously without a huge cache was AMD's K7s, AMD's K7s are AMD first Distributed Processing designs emulating compatible classical Intel's Symmetric Processing (Time-Share/Time-Division Processing).
All hub devices (time-share/time-division devices) can operate within a switching architecture without restriction. No switch devices (crossbar devices) can operate within a hub architecture without degraded performance restriction since all hub devices are inherently only synchronous by default, one time slice at a time.
Only retarded network managers used a network hub as the backbone where all the switches get connected to, it is always the hubs which get connected to a network switch that being used as the bapckbone.