Pairing memory size&speed across my 2x2 banks

By jhn_wagoner
Dec 17, 2007
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  1. I have four 184 pin-DIMM sockets
    Supports Dual Channel DDR 400 ECC/non-ECC un-buffered memory
    Suppports up to 4GB RAM
    Existing Memory is OCZ DDR PC-3200 / 400MHz / Value Series / Dual Channel .

    New memory is Micron/Crucial 1GB PC2700UNBUFF PBF /333Mhz

    This would make a total of 3GB and totally populate the MBD with 4 sticks.

    I spent$70 (if I get the rebates) for the new 2GB of memory.

    Questions:
    1. Do I keep the faster 400MHz 1GB memory in Bank A
    2. Do I need all 400MHz memory? (I can return the new stuff)
    3. Can I overclock any of this if it is better matched?

    Any comments appreciated. This is a noobe post. (My first post.)

    MY motherboard is ABIT KN8 SLI(NF-CK804) Socket 939
    AMD Athlon 64 Processor 3700+ 2200MHz

    THANKS ALL!
  2. Rik

    Rik Banned Posts: 4,985

    You should never ever mix different speeds of ram unless you like dealing with bsod's and instability issues.
  3. jhn_wagoner

    jhn_wagoner Newcomer, in training Topic Starter

    Some good info, stolen from "thebleedingedge" where it was stolen from elswhere...
    -----------------------------------------------------------------------

    Below is a copy/paste from an article on memory timings, it covers most of them; there are others if you want to dig into it deeper.... Google is your friend ;)

    CAS (tCL) Timing: CAS stands for Column Address Strobe or Column Address Select. It controls the amount of time in cycles between sending a reading command and the time to act on it. From the beginning of the CAS to the end of the CAS is the latency. The lower the time of these in cycles, the higher the memory performance.

    e.g.: 2.5-3-3-8 The bold “2.5” is the CAS timing.


    tRCD Timing: RAS to CAS Delay (Row Address Strobe/Select to Column Address Strobe/Select). Is the amount of time in cycles for issuing an active command and the read/write commands.

    e.g.: 2.5-3-3-8 The bold “3” is the tRCD timing.


    tRP Timing: Row Precharge Time. This is the minimum time between active commands and the read/writes of the next bank on the memory module.

    e.g.: 2.5-3-3-8 The bold “3” is the tRP timing.


    tRAS Timing: Min RAS Active Time. The amount of time between a row being activated by precharge and deactivated. A row cannot be deactivated until tRAS has completed. The lower this is, the faster the performance, but if it is set too low, it can cause data corruption by deactivating the row too soon.

    tRAS = tCL + tRCD + tRP (+/- 1) so that it gives everything enought time before closing the bank.

    e.g.: 2.5-3-3-8 The bold “8” is the tRAS timing.

    (The 2.5-3-3-8 figure is just an example for memory timings.)

    These are the four timings that you would see when memory is being rated. It is in the order of CAS-tRCD-tRP-tRAS. The lower these timings, the higher the performance of the memory. Some motherboard manufactors (DFI for example) list the timings in their bios CAS-tRCD-tRAS-tRP.

    Certain memories can take tighter (lower) timings at higher speeds. These are the more expensive memory modules out of the bunch. There are also other timings to consider in your BIOS. Not all boards will have options like these.

    [page=Other Timings & Conclusion]
    Other Timings.

    Command Rate: Also called CPC (Command Per Clock). The amount of time in cycles when the chip select is executed and the commands can be issued. The lower (1T) the faster the performance, but 2T is used to maintain system stability. On Intel based machines, 1T is always used where the number of banks per channel are limited to 4.


    tRC Timing: Row Cycle Time. The minimum time in cycles it takes a row to complete a full cycle. This can be determined by; tRC = tRAS + tRP. If this is set too short it can cause corruption of data and if it is to high, it will cause a loss in performance, but increase stability.


    tRRD Timing: Row to Row Delay or RAS to RAS Delay. The amount of cycles that it takes to activate the next bank of memory. It is the opposite of tRAS. The lower the timing, the better the performance, but it can cause instability.


    tRFC Timing: Row Refresh Cycle Timing. This determines the amount of cycles to refresh a row on a memory bank. If this is set too short it can cause corruption of data and if it is too high, it will cause a loss in performance, but increased stability.


    tRW Timing: Write Recovery Time. The amount of cycles that are required after a valid write operation and precharge. This is to insure that data is written properly.


    tRTW/tRWT Timing: Read to Write Delay. When a write command is received, this is the amount of cycles for the command to be executed.


    tWTR Timing: Write to Read Delay. The amount of cycles required between a valid write command and the next read command. Lower is better performance, but can cause instability.


    tREF Timing: The amount of time it takes before a charge is refreshed so it does not lose its charge and corrupt. Measured in micro-seconds (µsec).


    tWCL Timing: Write CAS number. Write to whatever bank is open to be written too. Operates at a rate of 1T, but can be set to others. It does not seem to work with other settings than 1T on DDR. DDR2 is different though.

    ------------------------------------------------------------------

    AND see wikipedia "RAM_latency" (Site wouldn't let me include link, I'm a NOOBEE!)



    My apologies if I am consuming too much bandwidth. ;?
  4. pdyckman@comcas

    pdyckman@comcas Newcomer, in training Posts: 718

    I didn't read all that you have written but will advise that when you mix memory, the total speed will be that of the slowest ram. Bes that you run all PC-3200.
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