Micron Technology has developed a DRAM architecture that combines a new capacitor with the 6F cell design, resulting in a die size reduction of 18 to 20 percent.
"Speaking at the 2004 Symposium on VLSI Technology here on Tuesday (June 15), Fred Fishburn, a process integration manager based in Boise, Idaho, said the 6F cell size is 25 percent smaller than the 8F designs used by most DRAM makers. "F" refers to the smallest printable feature size of the lithography used in the process. In this case, Micron is using a 78-nm half pitch to create a cell size of 0.36 microns2."
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