Covered topics include the new processor's triple-core design, deep pipeline, lack of an instruction window, and expected performance. Also covered is procedural synthesis, a technology used to make optimal use of system bandwidth and main memory by dynamically generating lower-level geometry data from statically stored higher-level scene data. Additionally, Xenon's revolutionary use of caches is covered in detail.
Xenon invests programmers with an unprecedented level of control over how their applications use the caches. Insofar as they can fall under the explicit control of the programmer, the Xenon's caches, and its L2 cache in particular, can function remarkably like the "local storage" that's attached to each of the Synergistic Processing Elements (SPEs) in IBM's Cell processor.
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