AMD updates roadmap for new Opterons

By Justin Mann on February 6, 2007, 1:02 PM
AMD's roadmap has been updated to include their new series of Quad-core Opterons. It has details on the various upcoming chips, in the 1000, 2000 and 8000 series. Starting off with several revisions of the Barecelona core (the SE, standard and HE models), all the models rely on independent L2 cache and a shared on-die L3 cache. They also will be using HyperTransport 1.0 at first, instead of the newer 3.0, which is odd but will be adjusted as newer successions are released.

The older manufacturing processes are starting to show their age, with the Opteron SE's TDP at around 120W, considerably higher than what we're used to seeing from AMD. The 1000 series will be based off the Budapest core, and will support HyperTransport 1.0 and 3.0.

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