In the new structure, pillars of stacked memory elements pass vertically through multi-stacked layers of electrode material and utilize shared peripheral circuits. The innovative design is a potential candidate technology for meeting future demand for higher density NAND flash memory.
Current stacking technologies simply stack two-dimensional memory array on top of another and repeating the same set of processes, indeed achieving increased memory density but at the cost of longer, more complicated manufacturing processes. Toshiba's new array increases density without increasing chip dimension, circumventing the limitations of the current stacking technologies. Toshiba will further develop this technology to the level where it matches current structures in terms of security and reliability.