TSMC announces a handful of 3nm process nodes, N2 coming in 2025

Tudor Cibean

Posts: 119   +8
Staff
In a nutshell: TSMC has just announced its entire lineup of 3nm class nodes launching over the next three years. Its new FinFlex tech will give chip designers even more flexibility to optimize each standard cell for the desired power consumption, performance, and density.

TSMC has just unveiled its entire N3 family of process nodes. Chip designers such as AMD, Apple, Nvidia, and even Intel will use these nodes over the next few years to fabricate their bleeding-edge chips.

The Taiwanese company has a total of five different 3nm class nodes. N3 will begin high-volume manufacturing later this year, with the first chips expected to reach customers early next year. N3E will launch later with performance and efficiency improvements, higher yields, but slightly reduced logic density.

Around 2024, TSMC will bring out N3P, which focuses on performance improvements. N3S, which wasn't featured in TSMC's roadmap, was only briefly mentioned in conversation by SVP Kevin Zhang.

Finally, N3X will come out about a year later and allow for extremely high performance at higher voltages, with efficiency and costs taking the back seat. This approach is similar to the 5nm class N4X process starting volume manufacturing next year.

TSMC's N3 and N3E nodes will also support the company's new FinFlex tech. Currently, chip designers have to pick one library for each block within an SoC. With FinFlex, they won't have this limitation and will be able to mix and match different libraries within each block.

They can use 2-1 (double-gate single-fin) FinFETs in some parts in order to reduce power consumption and die size (cost) and opt for 3-2 FinFETs in other areas where maximum performance is paramount. Meanwhile, 2-2 FinFETs provide a balance of size, performance, and power consumption.

TSMC also mentioned its upcoming N2 process node, which will use gate-all-around field-effect transistors (GAAFETs), with plans to start volume manufacturing in the second half of 2025.

Compared to N3E, it will reportedly draw 25-30 percent less power at the same frequency and allow for 10-15 percent more performance with the same power consumption and transistor count. Meanwhile, chip density will reportedly increase by over 10 percent.

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VitalyT

Posts: 6,277   +6,846
If TSMC were to announce, they are now using 1nm process, who could tell whether it is true or they are lying? Who is regulating these guys, to know for sure (my guess - nobody)?

It's not like you can look at their product and tell what process was used. And maybe that's the point, pushing fancy PR-s that nobody can argue against.
 
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Revolution 11

Posts: 136   +174
If TSMC were to announce, they are now using 1nm process, who could tell whether it is true or they are lying? Who is regulating these guys, to know for sure (my guess - nobody)?

It's not like you can look at their product and tell what process was used. And maybe that's the point, pushing fancy PR-s that nobody can argue against.
You are a bit late to this complaint. No one in the industry is using accurate size dimensions as the basis for naming a node for more than a decade now. The customers that use fabs only care about power, performance, and area of their chips. TSMC, Samsung, etc, all of these fabs are delivering the metrics that actual customers do care about.
 

kiwigraeme

Posts: 1,123   +822
Trying to make sense of bottom graph .
So this graph says as you increase power you get a better speed return ( ie upward swing )

You would think more resistance and less power - well someone here could explain it to me- then again High Voltage lines =increase efficiency of power around our countries I believe - but one is quite of macro vs super micro
 

BadThad

Posts: 1,102   +1,300
They are quickly approaching the limits of lithography and it's electro migration issues.