Samsung develops new stacking process for DRAM

By on April 24, 2007, 2:10 PM
Samsung announced it has developed an all-DRAM stacked memory package using ‘through silicon via’ (TSV) technology, which supposedly results in memory packages that are faster, smaller and consume less power. Normally memory chips are connected by wire bonding, which requiring vertical spacing between dies. Samsung’s WSP technology uses micron-sized holes made vertically in the silicon to connect the memory circuits directly with a copper filling, eliminating the need for gaps.

“The innovative TSV-based MCP (multi-chip package) stacking technology offers next-generation packaging solution that will accommodate the ever-growing demand for smaller-sized, high-speed, high-density memory,” said Tae-Gyeong Chung, vice president, Interconnect Technology Development Team, Memory Division, Samsung Electronics. “In addition, the performance advancements achieved by our WSP technology can be utilized in many diverse combinations of semiconductor packaging, such as system-in-package solutions that combine logic with memory.”
Samsung's WSP technology is meant not only to reduce the overall package size, but also permit chips to operate faster and use less power. While all of this sounds quite interesting, the press release gives the hint that this technology is designed for next generation computing systems in 2010 and beyond.




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