The PCI Special Interest Group (PCI SIG) says it expects to finalize the PCI Express (PCIe) 3.0 standard by November 2010. The 3.0 specification is due in the fourth quarter of 2010, but now we know it's slated for 60 days after the PCI SIG released version 0.9, which was posted in mid-August, according to EE Times. Furthermore, Intel is already gearing up to implement the new high-speed interconnection into its Sandy Bridge processors for servers.
PCIe 3.0 has numerous advantages over existing bus specifications: it will operate at an 8GT/s bit rate (effectively double PCIe 2.0's bandwidth), will have different electrical models, and will move to 128-bit and 130-bit encoding schemes (the 8-bit and 10-bit scheme is no longer required). Most importantly, it will be compatible with version 2.0.
We can expect that manufacturers of high-end hardware (including next-generation Ethernet switches, graphics cards, and solid-state drives) will be among the first to implement PCIe 3.0 into their chips. Prototypes featuring PCIe 3.0 interconnection will start undergoing testing in early 2011, but the PCI SIG will only release tools to validate designs and start interoperability workshops in mid-2011 and won't complete a specification for testing 3.0 products until 2012. Typically, products using a new version of PCIe are available about a year after the spec becomes final, though some companies might jump the gun to get the bandwidth gains as soon as possible; in other words, next year isn't out of the question.