Startup claims 100x more efficient processor than current CPUs, secures $16M in funding

[zohaibahd]

Forward-looking: Power efficiency is the name of the game these days, and every chip designer strives to squeeze more performance out of less energy. A secretive startup called Efficient Computer Corp. claims to have taken that to a whole new level with their newly announced processor architecture.

Efficient Computer emerged from stealth mode this week, revealing their "Fabric" chip design. According to the company, this novel CPU can provide performance on par with current offerings, while using a tiny fraction of the electricity. They claim to be 100 times more efficient than "the best embedded von Neumann processor," and 1,000 times more economical than power-intensive GPUs. If true, those would be mind-blowing improvements.

In a press release, Efficient Computer announced that it has already implemented the Fabric processor architecture in its 'Monza' test system on a chip (SoC).

So what's their secret sauce? The details get pretty technical, but the key idea behind Fabric is optimizing for parallelism from the ground up. General-purpose CPUs are incredibly complex, carrying around tons of legacy cruft to maintain backwards compatibility. Efficient Computer strips all that away and uses a simplified, reconfigurable dataflow architecture to execute code across numerous parallel computing elements.

The innovative design stems from over seven years of research at Carnegie Mellon University. It exploits spatial parallelism by executing different instructions simultaneously across the physical layout of the chip. An efficient on-chip network links these parallel computing elements.

Efficient's software stack also supports major embedded languages such as C, C++, TensorFlow, and some Rust applications, enabling app developers to quickly recompile their code for the Fabric architecture. The startup indicates that Fabric's compiler was "designed alongside the hardware from day one."

Nevertheless, this need for software recompilation could limit mainstream adoption. Recompiling every application is challenging for more conventional consumer devices. So, at least initially, the target markets are specialized sectors such as health devices, civil infrastructure monitoring, satellites, defense, and security – areas where the power advantages would be most valuable.

Under the hood, Fabric presents a unique approach to parallel computing. While Efficient Computer is tight-lipped about the specifics of the processing architecture, their descriptions hint at a flexible, reconfigurable processor that can optimize itself for different workloads through software-defined instructions.

The company recently locked down $16 million in seed funding from Eclipse Ventures, likely aimed at launching their first Fabric chips. Efficient Computer reports having already inked deals with unnamed partners and are targeting production silicon shipping in early 2025.

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https://www.techspot.com/news/102201-startup-claims-100x-more-efficient-processor-than-current.html

 

[scavengerspc]

Fine, but will it play Cry... Oh, screw it.

 

[ZedRM]

This looks promising. Hopefully they can pull it off for mass production.

 

[HardReset]

With limited information, does not sound anything special. It's well known for decades that CPUs are pretty bad for paraller workloads. GPUs are better but still quite bad. Even comparing this type of paraller maximizer against CPUs and GPUs pretty much tells everything.

Against GPUs this may be OK. Against ASICs it's only advantage is probably ability to use standard compilers and/or ability to use on multiple purposes.

From limited information, this sounds like programmable ASIC-like chip. It probably wll have some use but because ASICs will still be more efficient, there is too much hype right now.

 

[WhiteLeaff]

Where are the tests? Where's the technical information? Show at least one valid comparison. It's not even worth writing an article about such a vague announcement.

Anyone can say anything and start their own leeching startup to live off the necks of investors
Ps: U$ 16M won't even pay for the development of a 14nm chip. lol

 

[SixTymes]

Now a days parallel coding is fairly easy to process. That's why many programs off load to GPU's. Lets see the stats on these for branched chain coding, and if its still 100x then I'll be impressed. Until that happens, yawn.

 

[kiwigraeme]

Where are the tests? Where's the technical information? Show at least one valid comparison. It's not even worth writing an article about such a vague announcement.

Anyone can say anything and start their own leeching startup to live off the necks of investors
Ps: U$ 16M won't even pay for the development of a 14nm chip. lol

Yeah I thought the 16M was a joke as well .maybe people responsible looking for large payout.

Given that I think if approximately true - has great potential in autonomous devices- with huge inputs .
Given that a whole new language would be find

Surely US defense department would be interested - Seeing current conflict , Drones etc need to be protected vs jamming, GPS hacking etc

I think people forget in how many tiny cpus/controllers in the world - in every day things
Even conservation/monitoring

Musk could use this for a rat to power it's neural link if so little power

Flip side "1984"- small hard to find longlife ( or permanent with solar/sound/compression( eg by cars )/wifi power source ) monitoring

 

[Endymio]

Yeah I thought the 16M was a joke as well .maybe people responsible looking for large payout.

This is normal for first-round funding; it's just enough seed capital to pay salaries and keep the doors open, while they put together something solid enough to attract Round Two investors. I imagine they're working on a software simulator now to verify performance, as well as an actual recompile of some existing software.

 

[ScottSoapbox]

This is normal for first-round funding; it's just enough seed capital to pay salaries and keep the doors open, while they put together something solid enough to attract Round Two investors. I imagine they're working on a software simulator now to verify performance, as well as an actual recompile of some existing software.

So glad someone here understands funding rounds. Cheers.

 

[Disiw]

This is normal for first-round funding; it's just enough seed capital to pay salaries and keep the doors open, while they put together something solid enough to attract Round Two investors. I imagine they're working on a software simulator now to verify performance, as well as an actual recompile of some existing software.

You are right. Thats how it usually work.

 

[quadibloc]

They're not breaking the laws of physics - or promising to. After all, we already know that GPU computing is a lot more energy-efficient than CPU computing. So this chip appears to be an attempt to apply the basic technology of the GPU to a more flexible architecture. Perhaps a little like what the Xeon Phi would have been, if it were based on a very simple RISC architecture instead of x86.

 

[maxxcool7421]

""So what's their secret sauce? The details get pretty technical, but the key idea behind Fabric is optimizing for parallelism from the ground up""

Already been tried, it was the single worst cpu Intel ever made. Itanium.

 

[erickmendes]

Fine, but will it play Cry... Oh, screw it.

Damn I'm late...

 

[redgarl]

Another Theranos...

My god, the investors are dumb to think this can even be possible.

Efficiency is linked heavily to the process node. Not even this, but if it was evenly possible, then the big chip makers would already found out.

 

[jpvalverde85]

If you're old enough you may remember Transmeta, the Crusoe and Efficeon processors. Those worked thru a software abstraction layer or VM over a VLIW hardware design (like Itanium later), targeted x86 compatibility but could also execute other code. This chips actually make it to the market, worked, were more efficient, but also they were a bit slower compared to the competition, and never leave their niche market.
This may be a respin or rethink of such idea, but hardly they will be able to beat a 14900KS on performance alone, yet efficience is becoming a strong trend, they may be have some big market there on server hardware.

 

[Endymio]

Efficiency is linked heavily to the process node. Not even this, but if it was evenly possible, then the big chip makers would already found out.

Um, efficiency is linked even more closely to the architecture. Note that GPUs are -- at the relatively same power budget -- more than 100X as fast as CPUs on certain problem sets, due primarily to their fully SIMD architecture.

I'll also note that Jensen himself has stated that, out of the 1000X performance increase NVidia's GPUs have been over the last decade, only 2.5X of that came from process improvements; the rest from architectural enhancements.

 

[Lounds]

I think the industry is already leaning towards RISC as the next major ISA for CPUs. I'll be very surprised if this becomes mainstream as there's a lot of legacy software out there.

 

[HardReset]

I'll also note that Jensen himself has stated that, out of the 1000X performance increase NVidia's GPUs have been over the last decade, only 2.5X of that came from process improvements; the rest from architectural enhancements.

As I stated earlier in this forum, Jensen talks BS. For example GTX980Ti vs RTX4090. Clock speed is up 2.5X and transistor count up 10X. Typical Jensen PR BS as usual.

I think the industry is already leaning towards RISC as the next major ISA for CPUs. I'll be very surprised if this becomes mainstream as there's a lot of legacy software out there.

Almost every CPU out there is internally RISC already. x86 compatibles included.

 

[scavengerspc]

For example GTX980Ti vs RTX4090. Clock speed is up 2.5X and transistor count up 10X. Typical Jensen PR BS as usual.

But I'm pretty sure they are up that much. Well, close.

EDIT
I checked Techpowerup. 980Ti - 4090
Base clock 1000 - 2235
Boost clock 1076 - 2520
Transistors 8,000 million - 76,300 million

 

[Endymio]

But I'm pretty sure they are up that much. Well, close.

Exactly. The process improvements have granted a bit less than a 2.5X improvement in clock speed. The transistor count is up by a factor of 8 -- but the power draw has risen by nearly 4X, meaning the efficiency is up by nearly the same 2.5X too. Yet on an AI training workload, the performance has risen by nearly 1000.

 

[HardReset]

Exactly. The process improvements have granted a bit less than a 2.5X improvement in clock speed. The transistor count is up by a factor of 8 -- but the power draw has risen by nearly 4X, meaning the efficiency is up by nearly the same 2.5X too. Yet on an AI training workload, the performance has risen by nearly 1000.

And that AI training has come with zero increase on transistor count, no? Nvidia just made better use of fixed transistor count, oh wait...

In other words, without larger transistor count architectural improvements would have been much much harder. Same with CPUs. While AMD has made architectural improvements since Zen, without better manufacturing processes (stuck with GF 14LPP) die size would be too large to make any sense.

 

[Endymio]

And that AI training has come with zero increase on transistor count, no? Nvidia just made better use of fixed transistor count, oh wait...

I'm not sure why you keep harping on this point like it's significant. The entire history of chip design has been about architecting additional transistors to increase IPC. There were no technical reasons that a billion-transistor chip couldn't have been designed in 1990 -- the reasons were purely economic. But what couldn't have been done in 1990 was to clock a chip at multi-ghz speeds, as we do today. Why? The process technology wouldn't allow it.