The technology is implemented in industry-standard DDR3 devices, and utilizes conventional module infrastructure. It enables power savings in systems by partitioning modules into multiple independent channels that share a common command/address port.
Threaded modules support 64-byte (512-bit) memory transfers at full bus utilization, which results in efficiency gains of up to 50% compared to regular DDR3 modules. Additionally, threaded modules are activated half as often, resulting in 20% less power consumption.
The companies are expected to show off the new technology in a "static demonstration" at the Intel Developer Forum in San Francisco this week.