The traditional scaling of semiconductor manufacturing processes died somewhere between the 130- and 90-nanometer nodes, Bernie Meyerson, IBM's chief technology officer, told an industry forum.

Meyerson expanded on his scaling-is-dead theme here, saying CMOS has hit a wall in terms of power consumption. He said industry faces a similar transition to the one faced when moving to CMOS from bipolar logic. A new problem is the lack of mature alternative transistor logic technology.

Read more: EETimes (http://www.eetimes.com/semi/news/showArticle.jhtml;jsessionid=EHHZDWX2DW4S2QSNDBGCKHY?articleID=19502091).