Connecting the dots: Intel is trying to reset its data center strategy on two tracks at once. On one side, it is rolling out Xeon 6+ Clearwater Forest, an all-E-core design built on the new Intel 18A process that pushes core counts up to 288 per socket. On the other, it is laying the groundwork for Xeon 7 Diamond Rapids on a refined 18A-P process, with higher core counts, PCIe 6.0 support, and a major increase in memory bandwidth for the next wave of servers. Together, these moves show how Intel is shifting its competitive focus toward core density, chiplet architecture, and process technology rather than raw clock speeds or thread counts.
In the near term, Xeon 6+ Clearwater Forest is the part that matters. Formerly known simply as Clearwater Forest, the family uses only E-cores and scales up to 288 Darkmont cores per socket, along with 576 MB of L3 cache.
The flagship Xeon 6990E+ is built for density first. In dual-socket systems, it can reach 576 cores, putting it squarely in the sights of hyperscalers and operators building large fleets of cloud or network servers that prioritize per-rack throughput over single-core performance.
Intel says the 6990E+ delivers around 30% higher performance per thread and 30% better performance per thread per watt than AMD Epyc 9965.
Xeon 6+ is Intel's most aggressive disaggregated server CPU to date. It combines 12 CPU chiplets built on Intel 18A, each with 24 Darkmont E-cores and no Hyper-Threading, arranged on three base tiles manufactured on Intel 3 that handle L3 cache and memory logic.
Two separate I/O chiplets, this time built on Intel 7, handle connectivity. All of the tiles are linked on-package through 12 EMIB 2.5D bridges embedded in the substrate. The result is a heavily chipletized design that increases core density and cache capacity while keeping I/O on a more mature process node.
Platform support is more evolutionary. Xeon 6+ Clearwater Forest fits into existing Xeon 6 platforms via the LGA 7529 socket and can be deployed in single- or dual-socket servers. In a single-socket configuration, systems offer up to 12 DDR5 memory channels at up to 8000 MT/s, plus 96 PCIe 5.0 lanes, including 64 lanes for CXL 2.0.
Power envelopes are higher than the previous Sierra Forest generation: what previously topped out at 330W now ranges from roughly 300W on the low end to 450W at the top of the stack, bringing Intel closer to the highest-power AMD Epyc parts.
A lot of the Xeon 6+ Clearwater Forest story is not about the cores themselves, but about what is attached alongside them. Across the range, Xeon 6+ supports up to 16 on-die accelerators: four each for Intel QuickAssist Technology (QAT), Dynamic Load Balancer (DLB), Data Streaming Accelerator (DSA), and In-Memory Analytics Accelerator (IAA).
These blocks are designed to offload compression, packet steering, data movement, and analytics workloads that would otherwise consume CPU cycles. On the cryptography side, Intel has added instructions for SHA-512, SM3, and SM4, while also expanding its push into confidential computing using Intel SGX to isolate applications and Intel TDX to isolate virtual machines.
There is also a new telemetry feature aimed at operators who track power budgets as closely as they track performance. Xeon 6+ Clearwater Forest introduces Intel Application Energy Telemetry (AET), a hardware capability that can attribute energy usage to workloads, microservices, containers, VMs, applications, and, when needed, individual software threads.
According to Intel, Xeon 6+ is the first platform to support AET, and the company plans to carry the feature forward into future Xeon generations, with data center providers as its primary audience.
On paper, the performance uplift over the previous generation is substantial. Xeon 6990E+ shows a claimed 2.26× generational gain over the Xeon 6780E, which had half as many threads and a significantly lower TDP. Intel also reports an average efficiency improvement of 55%, with gains ranging from 30% on the Stream Triad memory bandwidth benchmark to 79% on Linpack.
In its internal testing, Intel says Xeon 6+ Clearwater Forest delivers roughly a 30% advantage in integer and floating-point throughput and about 38% higher efficiency. At around 40% CPU utilization, Intel's charts show the 6990E+ up to 30% more efficient than AMD Epyc 9965, though the company has not released full-die competitive benchmarks and has not published comparisons against newer Arm server chips such as Nvidia's Vera CPU.
There is, however, a clear trade-off in vector support. Xeon 6+ Clearwater Forest stops at AVX2 and does not support AVX-512 or any variant of AVX10. An Intel spokesperson confirmed to Tom's Hardware that AVX10 is not present in this generation, despite earlier expectations around AVX10.2. For some workloads – especially those that rely heavily on wide vector operations – this will push more of the processing burden onto accelerators or external GPUs.
While this generation focuses on shipping 18A silicon today, Intel is already signaling its next step with Diamond Rapids. The Xeon 7 family is now officially targeted for 2027 and will move to the 18A-P node, which Intel has described as a more mature revision of 18A with improved performance, power efficiency, and thermals.
At Computex, alongside the Xeon 6+ Clearwater Forest announcement, Intel said Xeon 7 Diamond Rapids would support PCIe 6.0, offer 50% more cores than Xeon 6, and double Granite Rapids' memory bandwidth. The company has dropped an earlier plan for an 8-channel memory variant and is now focusing solely on a 16-channel design. With Granite Rapids-AP topping out at 614 GB/s and Granite Rapids-SP at 409 GB/s, Diamond Rapids is expected to reach at least 818 GB/s, and potentially 1.2 TB/s. With second-generation MRDIMMs, Intel says it could approach 1.6 TB/s per socket.
On core counts, public guidance and earlier disclosures suggest a peak of around 192 cores, based on a 50% increase over the 128-core Granite Rapids-AP 6980P. Intel has pushed back against rumors of 256-core and 512-core variants, even as external reports continue to discuss high-core-count Panther Cove-based designs.
The company has not yet said whether Xeon 7 will bring back Hyper-Threading, though it has told investors it plans to "reintroduce multi-threading back into our data center roadmap." Intel expects to share more details on Diamond Rapids at Hot Chips later this summer.
The process shift from 18A to 18A-P is central to the story. Intel claims 18A-P delivers 9% higher performance at the same power, or reduces power consumption by 18% at the same performance level, while also improving reliability and voltage behavior.
Those changes are not only about Xeon; they are part of Intel's effort to position 18A-P as a node capable of attracting external foundry customers as well. Intel will need that headroom. AMD's Zen 6-based Epyc Venice chips are currently expected to arrive earlier, with up to 256 cores, 1.6 TB/s of memory bandwidth per socket, and a claimed 70% generational performance increase.
For now, Xeon 6+ Clearwater Forest and Xeon 7 Diamond Rapids look like stepping stones Intel will use until it shifts focus to the Coral Rapids generation, expected in 2028 and planned to reintroduce SMT and potentially deliver a faster rollout cadence.
