For example she said there's an 800MHz Sparc that out performs an Intel Dual core at 2.2 GHz.
That's because clock rate is not the be all and end all. It depends on what you do with each clock cycle. There are quite a few variables. You'll probably go over pipelining next so here's just a little illustration of the point.
Simplistically, modern processors use what are called pipelines arranged into a core, and nowadays it is also common to even have multiple cores in a single die. A die is the physical package for a processor.
When you compare chips, the pipeline efficiency is one part you look at to see which is fastest. Easiest illustrated with an example.
1) Say I have a processor that is "pipelined" and has 5 stages in the pipeline (call it Processor A). In ideal circumstances, it can be processing an instruction in each stage of the pipe. So it finishes 1 instruction per clock cycle and each instruction takes 5 clocks from start to finish.
2) Next I introduce a new architecture (call it Processor B) that has a clock speed 50% faster but each instruction takes 7 clock cycles to finish. As long as no instructions are dependent on ones that go before it, we just gained 50% performance at the cost of instruction completion latency. But that doesn't mean much when your clock rate is 2GHz! The latency is practically nothing.
3) Now we consider situations where some instructions need the results of others. This can cause the pipeline to "stall". E.g. A x B + C, let's say for argument sake and our processor has an instruction for add and an instruction for multiply.
Here processor A may have to wait up to 5 cycles for the multiply to finish before doing the add. Processor B may have to wait up to 7 clock cycles.
Back to your question about the Sparc vs the Intel dual core, there are many ways an 800MHz processor can "beat" a 2.2GHz dual core.
a) The Sparc may have more cores. You didn't specify but the SPARC may be 4 or 6 or 8 or more cores. Or it could be just 1. This is just one factor.
b) Each core can have many pipes (pipelines) in it. So when my example before mentioned pipelines, modern cores actually have multiple. There is no physical limitations to the number of pipelines other than the size and cost of the chip. Just like number of cores. The SPARC could have lots of pipelines compared to the dual core.
c) The SPARC could have instructions that are more efficient. E.g. for my example, what if one processor had an instruction that did the add and multiply in a single instruction? It could be more efficient than one that does not if the clock speed is not too slowed down too much.
Hope that helps!