Hi, anyone explain the following lines in the
/usr/share/lib/make/make.rules(symbols):

.c.a:
$(COMPILE.c) -o $% $<
$(AR) $(ARFLAGS) $@ $%
$(RM) $%
and
.c~.o:
$(GET) $(GFLAGS) -P $< > $*.c
$(CC) $(CFLAGS) -c $*.c
If you could, please, thank you

Someone's schoolwork again?

These are suffix rules and show what make is supposed to do when it is requested to process a source ending with .c and a target ending with .a for example.

rules are formed from a syntax object: action
.c.a: a rule to make a .A thing from a .C thing
$(COMPILE.c) -o $% $< an action to assemble it
$(AR) $(ARFLAGS) $@ $% an action to archive it
$(RM) $% an action to delete the .a thing once archived


.c~.o: rule to create a .o from a .c source
$(GET) $(GFLAGS) -P $< > $*.c action to fetch the source file
$(CC) $(CFLAGS) -c $*.c and action to compile it

understand, $(xxx) are macros defined elsewhere and therefore can literally be anything. I've suggested typical action knowing what the rule: imply.

Try google for 'GNU Make' for online reference material

Thank you,by the way I have one of the worst teachers and he did not do a
good job explaining.

MAKE is a wonderfull tool.
Normally the 'default' rules (ie those built into the product) just do the right thing,
but you can teach it how to do every step. The non-default rule that
is really neat is the ability to ensure that your copy of the source is up-to-date
with respect to the source management system (sccs, rcs, or cvs).

the rules are hierarchial, so each step of the process can be controlled by you.

typically, the first rule is all:

all: config, build, install

config:

build:

install: mkdirs, copyfiles, setperms

mkdirs:

copyfiles:

setperms:

the white-spaces between the rules are critical; they are the delimiters of the actions associated to the rule immediately above.

by this example, the following are all valid invocations of this makefile;

make all
make config
make build
make mkdirs

this ought to stimulate some reading and usage for the tool.

Thank you now its clear!

Eh, this all depends on the contents of Makefile.

Just to make sure:

Difference between My make.rules and Built in make.rules:
Mine: If I have my own make.rule file the make must comply to my rules,
and build the objects accordingly.

Built in: I dont have to worry about rules that the make is going by,
the only thing I need is write my own makefile with my own depencencies
and commands.

Basically correct. Be aware however, that your rules are overrides to the defaults. You override what you NEED and just leave the rest alone:-)

but of course. Should have been more clearly stated as
'for the sample rules above...'