Hot Intel teraflops MIC coprocessor action

[Archean]

Rajeeb Hazra, general manager of high performance computing at Intel, hosted a lunch briefing with journalists to show off two things. The first was that it has working silicon for the x86-based "Knights Corner" Many Independent Core (MIC) coprocessor that the chip giant will be pitching as an alternative to using GPU coprocessors in x86 clusters.

Secondly, Intel has ten machines on the Top 500 list using the forthcoming "Sandy Bridge-EP" Xeon E5 processors, and they have a performance advantage over the new "Interlagos" Opteron 6200 processors that were launched earlier this week.

 

[dividebyzero]

If Anand's Interlagos .v. Magny Cours .v. Gulftown Xeon review (at least, Part 1) is any indication, the Opteron 6200's face an uphill battle against the Xeon E5's (at least the 8-core models), but they would seem handily placed for supplying CPU's for upgrading AMD based servers (using the existing C32/G34 sockets). From what I've read, the Opteron's might not be luring too many from the Intel camp even though the E5's require a new socket, since a great deal of software licence fee is on a per-core basis, and 16 Bulldozer cores don't match up particularly well against an equal number of SNB-E cores.
One thing in the Opteron's favour I expect will be power consumption and management. Sandy Bridge-E doesn't seem the most frugal of power consumers

Intel did not give out feeds and speeds for the new Xeon E5 line

Odd. The model line was announced 3weeks ago!