IBM removes Level 3 cache to improve performance

By Derek Sooman on February 23, 2005, 10:38 AM
IBM's new server chipset, which is designed to accommodate Intel's new four-way, 64-bit Xeon takes a new approach to boosting performance... eliminating Level 3 cache memory.

For some time now, it has been a trend in processor and memory sub-system designs to insert a small amount of high-speed memory (called a cache) for boosting processor to memory interface speeds. This new product instead uses a mainframe technique known as snoop bus filtering, which means processors in multi-way setups do not have to inspect each other's caches in the event of a cache miss but can instead go straight to main memory. It is claimed that this not only boosts performance, but that it can reduce costs by up to 40 per cent.




User Comments: 2

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bushwhacker said:
no L3 cache for XEON, weird
troygov said:
This is a great improvement in thinking.Save $, and improve performance by eliminatingthe unnecessary. Makes me wonder how many more improvementscan be accomplished by simplifying designs.
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