Sources say AMD didn't order enough 40nm wafers for Evergreen

User Comments: 10

1. October 22, 2009 8:15 PM
   

   red1776, Omnipotent Ruler of the Universe, said:

   Fudzilla does its best work with 'unnamed sources' I trust that site about as far as I can throw my neighbors wife.

   Reply
2. October 22, 2009 11:55 PM
   Guest said:

   The title is incorrect. It should be 300mm, not 40nm, wafers. Leave it to Fudzilla to not understand the difference between millimeters and nanometers. 40nm is smaller than a speck of dust and not visible to the naked eye.

   Reply
3. October 23, 2009 2:59 AM
   

   ¼ of a hotdog said:

   Fudzilla does its best work with 'unnamed sources' I trust that site about as far as I can throw my neighbors wife.

   That's got to be the best analogy I have ever heard!!!

   Reply
4. October 23, 2009 5:18 AM
   Guest said:

   Maybe this is a case of artificial shortage in order to keep prices high while nvidia does not release their new gpu generation. Then prices will certainly decrease to keep competition hardened.

   Reply
5. October 23, 2009 7:29 AM
   

   Vrmithrax, TechSpot Paladin, said:

   Guest said:

   The title is incorrect. It should be 300mm, not 40nm, wafers. Leave it to Fudzilla to not understand the difference between millimeters and nanometers. 40nm is smaller than a speck of dust and not visible to the naked eye.

   While I don't altogether ever trust the source of this article, they are actually correct in at least the wafer size listing. The Evergreen GPUs use 40nm Silicon technology, down from the 55nm they were using previously. The diameter of the wafer (like 300mm) does matter to a degree, to be sure it fits in the manufacturing proces. But wafer diameter does not matter nearly as much as the thickness for the process, that is the vital statistic that defines wafers. If it didn't matter, all of the chip manufacturers would be listing their length and width of their chips as the primary statistic, not the silicon thickness rating.

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6. October 23, 2009 7:51 AM
   Guest said:

   It should be fine to describe the wafers as 300 mm or 40 nm. In each case you are describing a different aspect of the chips.

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7. October 23, 2009 7:58 AM
   

   Rage_3K_Moiz, Sith Lord, said:

   40nm refers to the die\reticle size, not the wafers themselves.

   Guest is correct; the wafer size is 300mm. But most people don't really care about the semantics, since the general idea is about a silicon shortage, which everyone will get.

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8. October 23, 2009 9:11 AM
   Guest said:

   "The diameter of the wafer (like 300mm) does matter to a degree, to be sure it fits in the manufacturing proces. But wafer diameter does not matter nearly as much as the thickness for the process, that is the vital statistic that defines wafers. If it didn't matter, all of the chip manufacturers would be listing their length and width of their chips as the primary statistic, not the silicon thickness rating."

   You do understand that wafer size matters not when it comes to process technology used, right? I'm not sure you understand the difference between what is 300mm vs 55nm or 45nm or 40nm etc. When people say 45nm or 40nm, they are describing process technology used to "etch" features onto a silicon wafer. The reason 300mm is important to a wafer is because the larger the size the dies you can put on it. You can make 40nm processors on 200mm wafers if you want. But 300nm will allow you to have more processors on a single wafer, thus lowering your cost per processor.

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9. October 23, 2009 9:15 AM
   Guest said:

   Sorry, it should state "The reason 300mm is important to a wafer is because the larger the size the more dies you can put on it"

   Reply
10. October 23, 2009 9:44 AM
    

    Vrmithrax, TechSpot Paladin, said:

    Heh... I think my brain began the weekend a day early (Note to self: Do not comment or post prior to coffee intake). Wafer thickness is typically a set constant, determined by the diameter of the wafer... I was thinking of the lithography and layering processes, which determine the resolution of the IC components... The silicon wafer substrate really has no bearing on that resolution.

    At least I waited till Friday for a bonehead post

    Reply

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