AMD shows off more 3D-stacking technologies at Hot Chips 33

Soupreme

Posts: 36   +2
Staff
Forward-looking: 3D chip stacking technology has yet to arrive in a big way, with only Intel Foveros reaching the market in Lakefield CPUs, and some Zen3-with-vertically-stacked-cache products waiting in the wings. But at this year's Hot Chips symposium, AMD is already laying out where it intends to go from here, with ambitious ideas on how to apply the technology.

The 3D V-Cache shown off by AMD at Computex is the (relatively) simple addition of further L3 cache to a Ryzen 9 5900X, bringing around a ~15% performance uplift in games. The 3D-stacking arrangement let AMD use a production process that allows for more densely packed SRAM for the upper die, fitting 64 MB in the space directly above the 32 MB on the base die that had to be silicon suitable for both cache and compute.

This was all done using through-silicon vias (TSVs), connected with direct vertical copper-to-copper connections that pack far closer together than "traditional" microbump technology.

AMD claims a 9 micron bump pitch for their hybrid direct bonding technology; by comparison, Intel Foveros was working on the order of 50 microns when implemented in Lakefield, the main point of comparison used for AMD's claim of 3x efficiency gains and 15x higher density with its interconnects compared to the conspicuously unspecified "other 3D architecture."

Team Blue also have a pitch of 36 microns quoted for their upcoming Foveros Omni technology to be used in Meteor Lake CPUs, and 10 microns in Foveros Direct, a hybrid solution that more directly competes with what AMD's showing off here.

However, both are only slated to arrive in 2023, while AMD have stated that their 3D-stacked Ryzen chips will be in mass-production by the end of this year.

The company is also working with TSMC on more complex 3D stacking designs, with the ambition to stack CPU cores on one another, splitting macroblocks of a CPU (such as lower levels of cache) between different layers, or even going down to the level of circuit slicing.

Stacking compute silicon in particular brings unique difficulties in providing power to higher dies and removing heat from lower ones -- one of the reasons why AMD's 3D V-Cache is only layered on top of the base die's cache, leaving the CPU cores alone.

Of course, all of this depends on how much improvement can be brought in power, performance, area and cost (PPAC) metrics -- and, of course, if TSMC can continue to deliver their advanced packaging techniques in mass production.

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kiwigraeme

Posts: 541   +417
Silly question - could you also meaningfully cooled the cpu on the pin side , or from underneath the M/B?

Surely also someone can come up with a high tech solution - eg feed a liquid into porous cooling block - evaporates taking heat , condense & recycle + build in std model
 

umbala

Posts: 410   +576
Surely also someone can come up with a high tech solution - eg feed a liquid into porous cooling block - evaporates taking heat , condense & recycle + build in std model
Yeah, that's what we need. Complex and exotic cooling solutions with lots of failure points! :)
 

Watzupken

Posts: 329   +308
I don't know with all these stacking happening, will it eventually be a nightmare to cool the chips. Considering the chiplet design used by AMD for couple of gen, I feel the chiplets are pretty difficult to keep cool given the small surface area. Now with power requirement expected to go up further, and components being stacked, thermals may be a problem.
 

Inthenstus

Posts: 62   +73
TechSpot Elite
Silly question - could you also meaningfully cooled the cpu on the pin side , or from underneath the M/B?

Surely also someone can come up with a high tech solution - eg feed a liquid into porous cooling block - evaporates taking heat , condense & recycle + build in std model

Better yet, have the pins on the sides of the processor and the hear plates on the top and bottom of the processors.
 

kiwigraeme

Posts: 541   +417
Yeah, that's what we need. Complex and exotic cooling solutions with lots of failure points! :)
No just a simple closed loop that runs entirely off the heat from the CPU - just like precipitation cycle here on earth - been running for over a billion years as a closed loop
 

Puiu

Posts: 4,928   +3,796
TechSpot Elite
No just a simple closed loop that runs entirely off the heat from the CPU - just like precipitation cycle here on earth - been running for over a billion years as a closed loop
It could work, but the form factor would need to change and the benefits wouldn't be that great since most of the heat would come from the other side.

You are better of making a cooling system that gets as close to the dies as possible. (directly touching the die instead of the metal cover)
 
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Danny101

Posts: 1,848   +794
Sounds good. Sounds promising. This doesn't sound like a great solution for something like Threadripper with it's many cores.. Excepting, for nm shrinking and a light touch of this technology. For consumer use with lower core requirements, this sounds like a great solution. A lot will probably depend on your usage requirements. We're getting further away from jack-of-all-trades CPUs and more to specialized CPUs. You really have to do your homework now determining the best CPU and value for the dollar.