Japan, US partner on 2nm chip R&D and manufacturing

Shawn Knight

Posts: 14,321   +162
Staff member
In brief: Japan is looking to become a major player in the race to commercialize the next generation of chip technology and will partner with the US to realize its goal. According to a report from Nikkei Asia, private companies from the two countries will work together on research and mass production.

Each side has plenty to bring to the table. IBM, for example, showed off a 2nm design last year that could accommodate as many as 50 billion transistors on a chip the size of a fingernail. Japan, meanwhile, is home to several major chipmaking equipment makers including Canon and Tokyo Electron.

Joint research could begin as soon as this summer, and the first facility in the region is expected to be built between fiscal year 2025 and fiscal year 2027.

The publication notes that Japanese and US firms could establish an entirely new company to run the project, and that Japan's Ministry of Economy, Trade and Industry will partially subsidize R&D costs and capital expenditures.

According to Nikkei, the first wave of 2nm chips will likely be destined for data centers, quantum computers and flagship smartphones. They could also be useful in military applications, linking them directly to matters of national security.

Rival TSMC is widely regarded as the industry leader in next-gen chip production. The semiconductor giant is on track to start mass producing 3nm chips later this year and aims to have 2nm chips rolling off the assembly line by the end of 2025.

Image credit: Sergei Starostin

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kiwigraeme

Posts: 1,193   +872
Having watched a video on TMSC - you have to do something like 400 steps - each with a need to 99.99% success rate - as failures multiply .
It seems most skill is in applied experience.
Some people are just bad at making beer or even pancakes
 

Mr Majestyk

Posts: 1,348   +1,230
Is there a single element of the lithography that is anywhere near 2nm. Are even the line traces 2nm as no other component such as FinFET etc has features sizes within order of magnitude of 4nm let alone 2nm. Can they just stop with the BS naming?

Oh and fun fact: With EUV FABS costing many billions of dollars, a company has developed entangled photons lithography that only uses HeNe lasers to actually achieve 1nm feature sizes all for a whopping million dollars or so. The hardest part is producing enough entangled photons, which is not so hard now. I wonder if any of the big tech companies are taking this seriously