TSMC's performance-boosting 3nm N3P node on schedule for late 2024

[zohaibahd]

What just happened? The competition to produce the world's most advanced chips is heating up, and TSMC appears to be staying ahead of the curve. At its recent technology symposium, the semiconductor manufacturing giant provided an update on its latest 3nm processes, confirming that its performance-optimized N3P node is on schedule to enter mass production in the second half of 2024.

Building upon the successful rollout of its current-gen N3E process, the N3P node represents an optical shrink that promises heightened performance efficiency and improved transistor density. While N3E has already hit volume production, with TSMC boasting "great" yield rates on par with its mature 5nm technology, the upcoming N3P offers chip designers a next step forward.

According to TSMC executives, the N3P process has now finished qualification, with its yield performance tracking closely behind the N3E node it derives from. As an optical shrink, it maintains compatibility with N3E in terms of IP blocks, design rules, EDA tools, and methodologies – smoothing the transition for manufacturers.

But the key advantages lie in the enhanced specifications N3P brings to the table. Chip designers can expect a performance uplift of around four percent at the same power or a power reduction of approximately nine percent at matched clocks compared to N3E. Transistor density also gets a four percent boost for typical chip designs consisting of logic, SRAM, and analog components.

While the original N3 (or N3B) node had a relatively muted customer base focused on Apple's newest M-series chips, N3E will be widely adopted across TSMC's semiconductor client list.

As Moore's Law slows and miniaturization becomes exponentially more challenging, manufacturing innovations like N3P that boost transistor performance without relying on further scaling could prove pivotal. An industry official recently even predicted that 3nm processes will remain popular for an unusually long time.

Late last year, reports emerged of potential yield issues plaguing Samsung and TSMC. Sources indicated both firms struggled to surpass 60 percent yields, below viable levels for attracting vendors. Samsung's proclaimed 60 percent yield allegedly excluded SRAM components, while TSMC faced rumors of process optimizations lagging behind schedule after consumer complaints of iPhone 15 Pro overheating. Those problems seem to be in the past now, at least on the TSMC side of things.

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TSMC's performance-boosting 3nm N3P node on schedule for late 2024

 

[Endymio]

manufacturing innovations like N3P that boost transistor performance without relying on further scaling could prove pivotal....

As the article itself points out, it's basically an optical shrink of N3E -- there's a 2% minimum optical scaling -- and it can rise to a 4% shrink, depending on the mix of logic vs. analog on the chip. That's the entirety of the performance gain right there ... or it allows a slight voltage reduction, to get up to a 9% efficiency gain instead.

 

[kiwigraeme]

I saw a well done YT video on the development of a blue LED.

Though it won't happen as too many trade secrets, A doco on how to get say an early yield of say 10% to 90% would be quite interesting if done right. Anyone can make coffee,wine whatever etc but a lot of know how goes into getting the best. This is why say China stealing secrets is often not enough