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Well, one thing is certain, the nVidia reference spec has five POSCAPs and one MLCC array. Therefore, the cards with five or six POSCAPs are BELOW nVidia's spec and that IS the AIB partner's fault.
You are thinking of Igor's lab's image:
The image was made to show the possible choices. If you look at other capacitor locations, you can see the outline for either POSCAPs or an MLCC array in all 6.
If you read article, it doesn't state that 1 POSCAP is required. It simply states that either can be used in any of the 6 locations
Techpowerup comes to the same conclusion as well:
"Another reason for this, according to Igor, is the actual "reference board" PG132 design, which is used as a reference, "Base Design" for partners to architecture their custom cards around. The thing here is that apparently NVIDIA's BOM left open choices in terms of power cleanup and regulation in the mounted capacitors. The Base Design features six mandatory capacitors for filtering high frequencies on the voltage rails (NVVDD and MSVDD). There are a number of choices for capacitors to be installed here, with varying levels of capability. POSCAPs (Conductive Polymer Tantalum Solid Capacitors) are generally worse than SP-CAPs (Conductive Polymer-Aluminium-Electrolytic-Capacitors) which are superseded in quality by MLCCs (Multilayer Ceramic Chip Capacitor, which have to be deployed in groups)."
Mind you even if we didn't have 6 POSCAP designs, this issue is still occurring on cards with 1 or even 2. According to Igor, Nvidia did not give AIBs enough time to test or bin their cards so they were going into this pretty blind.