Rumor: Nvidia GeForce GTX 880 specs revealed

There are 288 ROPs and 94 TMUs
Makes no sense. When was the last time a GPU was built with a higher number of raster units that texture units?
Never.
Also, the core count is 3584
Nice try. On the 28nm process node at TSMC's transistor density that equates to ~ 650mm² - 670mm² die....that exceeds TSMC's maximum die size of 625mm²
TSMCinterposersize.006.png

The other alternatives are that:
1. Your "friend" is having you on
2. It's a wish list for a 16nm FinFET successor to GK110 rather than a 28nm Maxwell replacement for GK 104. In which case I'd say your friend is full of it since AFAIK the next large Nvidia GPU has only recently (last few weeks) been taped out on 28nm.
 
Makes no sense. When was the last time a GPU was built with a higher number of raster units that texture units?
Never.
[quote="Patrick Proctor, post: 1411960, member: 350304] Also, the core count is 3584
Nice try. On the 28nm process node at TSMC's transistor density that equates to ~ 650mm² - 670mm² die....that exceeds TSMC's maximum die size of 625mm²

You do know mass production of the 20nm process began in late April, right? It comes in about about 600mm² flat.

Second, the raster count outgrew the TMUs because upgrading the 384 bus to 512 was more difficult than anticipated. Some sacrifices had to be made, including making each raster unit half the bandwidth for efficient programmability. So you could in fact cut the raster number in half to see the number of 512 units. Then you account for inefficiencies of using the older units and to match performance you use more.
 
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You do know mass production of the 20nm process began in late April, right? It comes in about about 600mm² flat.
I also know that AMD definitively said no GPUs on 20nm (CLN20SOC), and Nvidia are 1. Known to be taping out on 28nm, and 2. aren't going to produce a 20nm GPU if AMD can't.
Second, the raster count outgrew the TMUs....
That's gibberish.
Using your numbers 3584 cores tied to 94 TMUs means 38.127 cores per TMU. How the hell can you get a decimal?
GK 110 : 240 TMU for 2880 cores = 12 cores per TMU. 192 cores per SMX
GM 107: 40 TMU for 640 cores = 16 cores per TMU. 128 cores per SMM
or maybe a look at another architecture...
Hawaii: 176 TMU for 2816 cores = 16 cores per TMU.

...and you want us to believe that not only is 38.12765957446809 significantly lop sided in comparison to accepted architecture, it's not even doable from a compute unit point of view.

:SMH:
 
I also know that AMD definitively said no GPUs on 20nm (CLN20SOC), and Nvidia are 1. Known to be taping out on 28nm, and 2. aren't going to produce a 20nm GPU if AMD can't.

That's gibberish.
Using your numbers 3584 cores tied to 94 TMUs means 38.127 cores per TMU. How the hell can you get a decimal?
GK 110 : 240 TMU for 2880 cores = 12 cores per TMU. 192 cores per SMX
GM 107: 40 TMU for 640 cores = 16 cores per TMU. 128 cores per SMM
or maybe a look at another architecture...
Hawaii: 176 TMU for 2816 cores = 16 cores per TMU.

...and you want us to believe that not only is 38.12765957446809 significantly lop sided in comparison to accepted architecture, it's not even doable from a compute unit point of view.

:SMH:
You do know the initial cards don't always fill out full specs, right? I point you towards the original titan which ALSO has a decimal in the core to raster count.

Finally, that link you posted (sucks for you since I am native German) is also rumors. There's no definitive proof, apart from the card I've seen with my own eyes.
 
You do know the initial cards don't always fill out full specs, right? I point you towards the original titan which ALSO has a decimal in the core to raster count.
ROPs aren't tied to compute units, which is why I took issue with the TMU count you posted...where you have a decimal where there can't be (3584 / 94)...unless of course the compute units are all different sizes :rolleyes:

You really think that a GPU is viable with 25% more cores than a Titan Black but with fewer texture address units than a GTX 760?

BTW: GTX Titan : 2688 Cores / 224 TMU's = 12 cores pre TMU. Unsurprising really since the Titan had 14 of the 15 SMX active... and of course there are 16 TMU's per SMX

There's no definitive proof, apart from the card I've seen with my own eyes.
Time for glasses pal. Maybe a course in understanding the graphics pipeline as well, since I swear if you're for real and not just putting on a "I can count to potato" act you really need it if this is any indication
Some sacrifices had to be made, including making each raster unit half the bandwidth for efficient programmability.
Little hint: ROPs use a pixels-per-clock measurement not a bytes-per-second measurement.

Thanks for the laughs.
/ Bookmarked for humour value....94 TMU, 288 ROP !...:D:D:D:D:D:D:D:D
 
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er·go·nom·ics(ûr′gə-nŏm′ĭks)
n.
1. (used with a sing. verb)

Ergonomic refers to efficiency of using an object, with emphasis to maximizing such and minimizing the discomfort of using the object. With reference to a video card that implies keeping the same size and power consumption.

P.S. Don't do that again, please...

No it doesn't, please don't misuse words just because they sound fancy.
 
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