AMD: Zen 3 is on track to launch in 2020 and looking great

[MaxSmarties]

I really hope so.
I’m planning on upgrading my i5-9600K @ 4.7 GHz with a Ryzen 7 4700X, in January 2021.
I’m curious about improvements.

 

[MaxSmarties]

6 months ago...
My Desktop: Intel/nvidia
My Laptop: Intel/nvidia
Son's PC: Intel/nvidia

Today:
My Desktop: AMD/AMD
My Laptop: AMD (APU)
Son's PC: AMD/nvidia

Your son’s PC seems to be the most balanced.
As an 5700XT owner I would say AMD GPUs aren’t there yet.

 

[Jerry in WA]

Your son’s PC seems to be the most balanced.
As an 5700XT owner I would say AMD GPUs aren’t there yet.

True, the 5700XT isn't as rock solid as my 1070 was, but it's not really been much trouble at all. And he games at 1080p ultrawide, so he's having a good old time.

I wanted to get a 2080Ti but decided to go 5700XT as a stopgap until the new cards arrive. (1440p ultrawide)

I forgot to mention I'd been running nothing but Intel/nvidia builds for 13 years until now. It's kind of nice to change.

 

[MaxSmarties]

True, the 5700XT isn't as rock solid as my 1070 was, but it's not really been much trouble at all. And he games at 1080p ultrawide, so he's having a good old time.

I wanted to get a 2080Ti but decided to go 5700XT as a stopgap until the new cards arrive. (1440p ultrawide)

I forgot to mention I'd been running nothing but Intel/nvidia builds for 13 years until now. It's kind of nice to change.

I don’t have any brand loyalty, but I see your point. My next game rig, in December/January, could be a Ryzen 7 4800X for instance (Intel isn’t doing really well lately).
I just don’t like the issues the 5700XT gave me in this 7 months of ownership (black screens mostly).

 

[DZillaXx]

Latency between CCX is probably still there as probably nothing changes except L3 cache that is shared with both 4-core groups (it might be no longer CCX) whereas on Zen/Zen+/Zen2 it's split.

This is still best we have

https://imgur.com/Dw4fFbk

and unfortunately that latency between 4-core groups is still there. To clarify: so far AMD hasn't said anything about "8-core CCX". They only said that 8 cores share same L3 cache that is totally different thing than "8-core CCX" that some sites tend to promote.

But picture above is about server version and desktop version might be different. With integrated memory controller like latest APU's perhaps.



AVX-512 support with 512-bit wide FPU units easily give that "around 50% improvement". In supported software of course.



Skylake is more effective on games primarily because overall memory latency is much lower. Zen2 with chiplets is purely server design after all. While chiplet design with IO die gives some advantages, like same memory latency for all chiplets, that hardly matters when there is only one chiplet.

Even if it isn't a 8-core CCX, which is why I said the details are not 100% clear. The Shared L3 cache would reduce CCX to CCX latency big time. As currently for one CCX to access the cache of the other CCX, it needs to go through the infinity fabric interface. It also eliminates the needs to have the same data in both cache pools. This is going to be a huge change.

Zen 2 already had some pretty big improvements in regards to memory latency, and Honestly isn't even that bad. The CCX to CCX memory latency is more than twice the latency on inner CCX communication. Which is why when you look at 4 core Zen 2 chips compared to high clocked 4 core Intel chips in video games, Zen2 is highly competitive leading in most titles. Games already scale past 4 threads no problem, which is why the Intel i5 chips have aged so poorly.

 

[HardReset]

Even if it isn't a 8-core CCX, which is why I said the details are not 100% clear. The Shared L3 cache would reduce CCX to CCX latency big time. As currently for one CCX to access the cache of the other CCX, it needs to go through the infinity fabric interface. It also eliminates the needs to have the same data in both cache pools. This is going to be a huge change.

Zen 2 already had some pretty big improvements in regards to memory latency, and Honestly isn't even that bad. The CCX to CCX memory latency is more than twice the latency on inner CCX communication. Which is why when you look at 4 core Zen 2 chips compared to high clocked 4 core Intel chips in video games, Zen2 is highly competitive leading in most titles. Games already scale past 4 threads no problem, which is why the Intel i5 chips have aged so poorly.

Right, just read that 8-core CCX many times even when there is nothing said about that. CCX-CCX latency will get lower but it will still be higher than latency between 4-core groups. Better for desktop than Zen2 but still mostly server side design.

Memory latency itself is not that bad. However there are huge L3 cache that must be checked before memory access, there is IF latency from memory controller to chiplet etc. I'd say Zen2 does well in some games because L3 cache is so huge it many times is able to hide bigger memory latency and Zen2 L1 instruction cache design (32kB, 8-way associativity) happens to be same as seen Intel's lineup since Sandy Bridge. Easy way to get some Intel-like optimizations for Zen2. While Intel put 48 kB L1 data to Sunny Cove, they still kept L1 instruction cache same, tells something.

I also agree that using more than 4 cores is starting to show. But it also raises question about putting just 4 cores into same group. But as this is server design, we may expect to see Renoir-style monolithic designs for desktop. Hopefully.

 

[neeyik]

Even if it isn't a 8-core CCX, which is why I said the details are not 100% clear. The Shared L3 cache would reduce CCX to CCX latency big time. As currently for one CCX to access the cache of the other CCX, it needs to go through the infinity fabric interface. It also eliminates the needs to have the same data in both cache pools. This is going to be a huge change.

This is what a Zen 2 CCD chiplet looks like from a Ryzen 5 3600 (source):

You can see the I/O system running horizontally through the middle, with two 4 core CCXs either sides of it. Within each CCX, every core has the same access (in terms of cycles) for the L3 cache blocks - there are 16 in total, each 4 MB in size.

Accessing the other CCX's shared cache has to be done via the I/O chiplet, there's no direct access to it, even though both CCXs are on the same die. Now to make the entire L3 cache fully unified, that would have to changed - and either all cores access the cache via the I/O (unlikely, as although the latency would be consistent across all cores, it would be worse than it currently is for a single CCX accessing its own L3 cache) or the CCX effectively becomes 8 cores.

 

[Gastec]

Today (July 8th 2020) Nvidia surpassed Intel to become the biggest chipmaker company in the world...this despite Intel making way more profits than Nvidia. Which begs the question, is there any future for CPU makers?

As long as a PC (desktop, workstation, laptop, etc) is made with motherboards and CPU's and all the other components, then there is a future.