AMD Zen 6 could hit 7 GHz and 24 cores in desktop CPUs

[GeoffreyA]

Intel didn't need Core or Core 2 to "save" them. Prescott successor Tejas was quite ready when Intel just decided Pentium M is better choice. Intel would have done just fine with Pentium 4 too. No idea where this Core saved Intel -thing comes from. Maybe Tejas existence was just ignored.

Because at same time AMD messed at least two architectures, probably three and Bulldozer was very rushed one. No real competition was coming from AMD even if Intel just continued with Pentium 4 line.

While Intel was not in dire straits financially, Core 2 brought them back after a few years of AMD hitting hard. Between 2003 and 2006, the K8 was generally the better CPU. It took Conroe to dethrone it in 2006. Later came the disappointing K10, and Bulldozer in 2012.

As for Tejas, there are no known samples of it, and with a pipeline of 40–50 stages, it would have been catastrophic in terms of IPC and made even Prescott blush. Had there been no Core 2, Intel would have been in a pickle.

 

[HardReset]

While Intel was not in dire straits financially, Core 2 brought them back after a few years of AMD hitting hard. Between 2003 and 2006, the K8 was generally the better CPU. It took Conroe to dethrone it in 2006. Later came the disappointing K10, and Bulldozer in 2012.

As for Tejas, there are no known samples of it, and with a pipeline of 40–50 stages, it would have been catastrophic in terms of IPC and made even Prescott blush. Had there been no Core 2, Intel would have been in a pickle.

Core 2 only looked "better" than AMD because it had much more L2 cache. AMD just couldn't afford large dies at that time. Therefore Tejas with large cache would have been more than "enough".

And I said "better" because, just like Intel Hybrid CPUs, Conroe was made for benchmarks. When L2 cache run out, it slowed down a lot. Also AMD was much "smoother" because of IMC. At east Anandtech confirmed that.

As for Tejas, confirmed samples existed. Also one sample was sold on ebay recently so Tejas was at least half read. Also because AMD somehow managed to waste around 10 years (Athlon64 architecture ready 1999, Bulldozer architecture "ready" around 2009), Intel had no real trouble because of that.

 

[GeoffreyA]

Core 2 only looked "better" than AMD because it had much more L2 cache. AMD just couldn't afford large dies at that time. Therefore Tejas with large cache would have been more than "enough".

And I said "better" because, just like Intel Hybrid CPUs, Conroe was made for benchmarks. When L2 cache run out, it slowed down a lot. Also AMD was much "smoother" because of IMC. At east Anandtech confirmed that.

As for Tejas, confirmed samples existed. Also one sample was sold on ebay recently so Tejas was at least half read. Also because AMD somehow managed to waste around 10 years (Athlon64 architecture ready 1999, Bulldozer architecture "ready" around 2009), Intel had no real trouble because of that.

It wasn't only the bigger L2 cache; Conroe was wider, had better branch prediction, and did more work, beating the Athlon 64 while lacking an IMC. Phenom II covered the ground but it was too late, because Nehalem had already been unleashed.

All CPUs slow down when going out of L2 (or L3 today), but the Athlon 64 simply had less execution power, and the improved latency of an IMC couldn't make up for it.

To be sure, AMD wasn't aggressive enough that decade. They had to go through the darkness of the Bulldozer era, passing through the fire so to speak, before reaching where they are today: executing relentlessly that Intel is struggling to keep up.

 

[HardReset]

It wasn't only the bigger L2 cache; Conroe was wider, had better branch prediction, and did more work, beating the Athlon 64 while lacking an IMC. Phenom II covered the ground but it was too late, because Nehalem had already been unleashed.

All CPUs slow down when going out of L2 (or L3 today), but the Athlon 64 simply had less execution power, and the improved latency of an IMC couldn't make up for it.

To be sure, AMD wasn't aggressive enough that decade. They had to go through the darkness of the Bulldozer era, passing through the fire so to speak, before reaching where they are today: executing relentlessly that Intel is struggling to keep up.

Again, Core 2 looked good when running benchmarks. However on "less optimal conditions" when CPU more easily runs out of cache, Core 2 just lagged smoothness and responsivity because it missed IMC. Athlon64 x2 or Core 2 Duo? No questions, Athlon64 was better for majority. Perhaps not for those who were amazed for Core 2 running simple benchmarks that fit on L2 cache (Pifast for example). Nehalem solved problem but came much later with bigger price tag.

Situation is exactly same with Intel Hybrid vs AMD. For most people AMD is better choice. Because Thread director Will mess things up and most people cannot (or couldn't) adjust settings properly. No matter what benchmarks say, that's how it is.

AMD was aggressive enough but execution just, something missed. There is naturally very little information about cancelled architectures between K8 and Bulldozer. At that time development was much more hit or miss, AMD missed too much.

 

[GTvon]

I almost feel bad for Intel.

I feel sorry for AMD. Even when they make gains in the market it doesn't move the stock price. Intel is doing much better though now.

 

[GeoffreyA]

Again, Core 2 looked good when running benchmarks. However on "less optimal conditions" when CPU more easily runs out of cache, Core 2 just lagged smoothness and responsivity because it missed IMC. Athlon64 x2 or Core 2 Duo? No questions, Athlon64 was better for majority. Perhaps not for those who were amazed for Core 2 running simple benchmarks that fit on L2 cache (Pifast for example). Nehalem solved problem but came much later with bigger price tag.

Situation is exactly same with Intel Hybrid vs AMD. For most people AMD is better choice. Because Thread director Will mess things up and most people cannot (or couldn't) adjust settings properly. No matter what benchmarks say, that's how it is.

AMD was aggressive enough but execution just, something missed. There is naturally very little information about cancelled architectures between K8 and Bulldozer. At that time development was much more hit or miss, AMD missed too much.

Respectfully, I disagree that the Athlon 64 X2 was a better choice than the Core 2 Duo, and I say that as a former K8 user who loved his 3000+.

Yes, the Thread Director and scheduler situation are a mess. Using a single core type, and ramping it up and down in power, is a better approach. Intel should scale up their E-cores to high performance, and use those alone. Ultimately, the P-cores' architecture descends from P6, and those legacy roots are doubtless holding back efficiency. Look at how efficient Ryzen was, being built from scratch.

 

[toooooot]

Sweet. Does anyone know what model is the motherboard in the picture.

 

[HardReset]

Respectfully, I disagree that the Athlon 64 X2 was a better choice than the Core 2 Duo, and I say that as a former K8 user who loved his 3000+.

Yes, the Thread Director and scheduler situation are a mess. Using a single core type, and ramping it up and down in power, is a better approach. Intel should scale up their E-cores to high performance, and use those alone. Ultimately, the P-cores' architecture descends from P6, and those legacy roots are doubtless holding back efficiency. Look at how efficient Ryzen was, being built from scratch.

Feel free to disagree. I still point out that while IMC did not necessarily show on all benchmarks, in normal use it made noticable difference. Nowadays basically every CPU has IMC so we can ask why Core 2 was good without it when at same time AMD had it?

High performance E cores would replace P-cores and not be E-cores anymore. But totally agreed that Intel failing to design high performance CPU from scratch is holding them back.

 

[GeoffreyA]

Feel free to disagree. I still point out that while IMC did not necessarily show on all benchmarks, in normal use it made noticable difference. Nowadays basically every CPU has IMC so we can ask why Core 2 was good without it when at same time AMD had it?

Core 2 was good without an IMC because of its execution resources: if I remember correctly, it had a four-wide dispatch vs. K8's three; micro-op fusion; a bigger out-of-order window; indirect branch prediction; more ALUs; and likely, lower-latency caches and higher load-store bandwidth. I can't remember the numbers, so this paragraph is open to correction, but if you put the two side by side, I'm sure Core 2 had more resources than K8.

 

[ryao1]

“ Zen 6 will implement a dual IMC configuration, but will retain the familiar two-channel DDR5 memory setup. This means users should not expect quad-channel memory support on mainstream platforms, but higher memory speeds are anticipated.”

Zen 4 and Zen 5 are quad channel, not dual channel. DDR5 has 2 channels per DIMM. This talk of retaining the two channel configuration is wrong.

By the way, I really wish that DDR5 had kept the DDR4 1 channel per DIMM configuration. This 2 channel per DIMM configuration is confusing people.

 

[ryao1]

I feel sorry for AMD. Even when they make gains in the market it doesn't move the stock price. Intel is doing much better though now.

AMD’s stock price between July 1, 2019 and today is +364.83%.

Intel’s stock price between July 1, 2019 and today is -51.27%.

VOO (the S&P 500 index) between July 1, 2019 and today is +109.23%.

Zen 2 launched on July 7, 2019. My stock application will not show me the difference between that and today, but overall, I would say that AMD’s stock has outperformed while Intel’s stock has underperformed, given their relative performance to the S&P 500 index. AMD’s stock reflects their market gains while Intel’s stock reflects its market losses.

 

[ryao1]

As for Tejas, there are no known samples of it, and with a pipeline of 40–50 stages, it would have been catastrophic in terms of IPC and made even Prescott blush. Had there been no Core 2, Intel would have been in a pickle.

Samples exist, but no one outside any of Intel has gotten them to POST:

 

[daffy duck]

There will always be something better around the corner.

Why would you need nova lake if you have arrow lake? If you dont do a huge amount of gaming, those chips should easily last you a decade. I will never understand the constant need to upgrade for 5-10% performance increases when, unless you're buying halo GPUs every 2 years a CPU will almost never be a bottleneck in a system until its really REALLY old.
Someone else that doesnt understand the difference between TDP and efficiency.

Arrow Lake is a flawed beta that's why. No one is buying. It has major issues due to poor design choice like moving memory controller off cpu tile causing large increase in latency and hence poor gaming. It's ringbus is much much slower than Raptor Lake too. Nova Lake brings massive changes as does Panther Lake.

It'd be like saying why would anyone get Zen when Bulldozer exists!

 

[gamerk2]

It goes back to the original Pentium Pro, or P6 microarchitecture. Later, Pentium M carried on from the Pentium III Tualatin.

Intel's aim with the Pentium 4 was to reach high clock speeds, projecting 10 GHz. To do this, they increased the pipeline stages, first to 20 in Willamette and Northwood, and 31 in Prescott. It had low IPC compared to the Athlon and Pentium III, and reached a dead end at 3.8 GHz, owing to power and heat.

The Core microarchitecture, carrying on from the Pentium M, saved them, returning to a shorter 14-stage pipeline, lower clock speeds, and higher IPC. AMD did not recover till Ryzen a decade later.

Ding. People forget how bad AMD was through the Core-Bridge era.

Prior to Ryzen releasing, AMD had outstanding debt due in a few months that was more then the total valuation of the company. Ryzen was literally AMDs absolute last chance for a rebound, and they nailed it. Had Ryzen failed, AMD would not be here right now.

 

[HardReset]

Core 2 was good without an IMC because of its execution resources: if I remember correctly, it had a four-wide dispatch vs. K8's three; micro-op fusion; a bigger out-of-order window; indirect branch prediction; more ALUs; and likely, lower-latency caches and higher load-store bandwidth. I can't remember the numbers, so this paragraph is open to correction, but if you put the two side by side, I'm sure Core 2 had more resources than K8.

It had more resources but again, lack of IMC means memory latency is abysmal. And still today, bad memory latency means no high performance CPU despite caches are from another world.

Core 2: 32+32 kB L1 + 3 MB L2 (for 2 cores)
Ryzen 9800x3D: 32+48 kB L1 + 2 MB L2 + 8
MB L3 + 24 MB "L4" (L3 and L4 are calculated for 2 cores, just for comparison)

If Core 2 really is "fine" without IMC, Zen 5 also shouldn't need any kind of fast DRAM access. What AMD then does? Zen 6 will have redesigned IO die to improve DRAM access.

Even Intel engineers admitted that not having IMC is very bad thing. They tried to reduce effect of that by putting more cache but even when comparing against Nehalem thats not very convincing. If AMD just didn't have IMC, then Core 2 would have been "fine" without it. But in practice it was evident that when Core 2 runs out of cache, AMD is just better choice. And those situations happen often outside benchmarks.

“ Zen 6 will implement a dual IMC configuration, but will retain the familiar two-channel DDR5 memory setup. This means users should not expect quad-channel memory support on mainstream platforms, but higher memory speeds are anticipated.”

Zen 4 and Zen 5 are quad channel, not dual channel. DDR5 has 2 channels per DIMM. This talk of retaining the two channel configuration is wrong.

By the way, I really wish that DDR5 had kept the DDR4 1 channel per DIMM configuration. This 2 channel per DIMM configuration is confusing people.

DDR5 is dual channel just because channel is only 33 bit instead 64. To be more precise, dual channel should be 128 bit memory bus. But if talking without numbers, it's accepted that 128 bit memory channel equals dual channel. Therefore single DDR5 module is still single channel and I will keep talking that way. It's just how original "definition" was and I stick with it.

It's same thing with effective clock speeds. Quad pumping 100 MHz bus "is" 400 MHz effective but when making clock speed adjustments, it's 100 MHz not 400 MHz. Safer to talk absolute values.

 

[Manoa]

Big thank to AMD to stay on socket a new IO die on same socket is KING

 

[AnilD]

“ Zen 6 will implement a dual IMC configuration, but will retain the familiar two-channel DDR5 memory setup. This means users should not expect quad-channel memory support on mainstream platforms, but higher memory speeds are anticipated.”

Zen 4 and Zen 5 are quad channel, not dual channel. DDR5 has 2 channels per DIMM. This talk of retaining the two channel configuration is wrong.

By the way, I really wish that DDR5 had kept the DDR4 1 channel per DIMM configuration. This 2 channel per DIMM configuration is confusing people.

Dual-channel DDR5 can use dual-rank DIMMs, leading to performance boosts that simulate some quad-channel benefits in certain workloads. But architecturally Zen 4 and 5 is still dual-channel.

 

[GeoffreyA]

It had more resources but again, lack of IMC means memory latency is abysmal. And still today, bad memory latency means no high performance CPU despite caches are from another world.

Core 2: 32+32 kB L1 + 3 MB L2 (for 2 cores)
Ryzen 9800x3D: 32+48 kB L1 + 2 MB L2 + 8
MB L3 + 24 MB "L4" (L3 and L4 are calculated for 2 cores, just for comparison)

If Core 2 really is "fine" without IMC, Zen 5 also shouldn't need any kind of fast DRAM access. What AMD then does? Zen 6 will have redesigned IO die to improve DRAM access.

Even Intel engineers admitted that not having IMC is very bad thing. They tried to reduce effect of that by putting more cache but even when comparing against Nehalem thats not very convincing. If AMD just didn't have IMC, then Core 2 would have been "fine" without it. But in practice it was evident that when Core 2 runs out of cache, AMD is just better choice. And those situations happen often outside benchmarks.

Having an IMC is better than not. According to Anandtech's Johan De Gelas, K8 would have had 15 to 20% lower latency than Core, not much, and this was offset by the faster, bigger caches, better prefetching, and weightier resources. Against NetBurst, K8 had a big advantage in terms of latency, but not much against Core.

Intel Core versus AMD's K8 architecture

www.anandtech.com

 

[GeoffreyA]

Ding. People forget how bad AMD was through the Core-Bridge era.

Prior to Ryzen releasing, AMD had outstanding debt due in a few months that was more then the total valuation of the company. Ryzen was literally AMDs absolute last chance for a rebound, and they nailed it. Had Ryzen failed, AMD would not be here right now.

It was a dark time for them, but they did it.

 

[HardReset]

Having an IMC is better than not. According to Anandtech's Johan De Gelas, K8 would have had 15 to 20% lower latency than Core, not much, and this was offset by the faster, bigger caches, better prefetching, and weightier resources. Against NetBurst, K8 had a big advantage in terms of latency, but not much against Core.

Intel Core versus AMD's K8 architecture

www.anandtech.com

That might be true for Some situations. But, any caches, not matter how big and fast, mean nothing when DRAM access is needed. At that point, DRAM latency and bandwidth is all that matters.And when it comes to that, Athlon64 X2 is jut smoother to use than Core 2 Duo.

Smoothness is very underrated thing. For most people, irritating situation possible is when something just chokes. When something works like molasses. And when Core 2 runs out of cache, then AMD is smoother. Like said on this article: https://www.anandtech.com/show/2715

And that is Best case scenario for Intel (background tasks minimized) that usually happens only when benchmarking.

 

[Puiu]

Arrow Lake is a flawed beta that's why. No one is buying. It has major issues due to poor design choice like moving memory controller off cpu tile causing large increase in latency and hence poor gaming. It's ringbus is much much slower than Raptor Lake too. Nova Lake brings massive changes as does Panther Lake.

It'd be like saying why would anyone get Zen when Bulldozer exists!

Panther Lake won't get major changes. It's an efficiency focused mobile CPU with which Intel is hoping of getting the current H performance to lower powered laptops (a combination of improved process node and some architecture efficiency gains).

As for Nova Lake, Intel's own slides say 10% ST improvements (ST, not IPC), with a huge 60% MT perf improvement (probably because of how many cores it will have). Even with the increased cache size, competing with Zen 6 x3D, just by looking at the specs of both, will be impossible for Intel. I just don't see them gaining 40-50% in games compared to arrow lake.

 

[GeoffreyA]

That might be true for Some situations. But, any caches, not matter how big and fast, mean nothing when DRAM access is needed. At that point, DRAM latency and bandwidth is all that matters.And when it comes to that, Athlon64 X2 is jut smoother to use than Core 2 Duo.

Smoothness is very underrated thing. For most people, irritating situation possible is when something just chokes. When something works like molasses. And when Core 2 runs out of cache, then AMD is smoother. Like said on this article: https://www.anandtech.com/show/2715

And that is Best case scenario for Intel (background tasks minimized) that usually happens only when benchmarking.

Fair enough. I haven't tested the Athlon 64 X2 and Core 2 Duo side by side, so can't comment. However, in that article, the Phenom II X4 is being used. Generally, K10 was faster than Core but behind Nehalem.

 

[dmoros]

I'm sticking with my 5800x3d until socket AM6 at the very lease, so every upgrade is one step closer tot he monster I'll build in 2030.

Same, my 5800X3D is still more than enough in 2025 for my usage (I dont do super high refresh rate gaming, and even on 144 Hz Displays I limit my fps to 90 fps to save power

 

[gamerk2]

Fair enough. I haven't tested the Athlon 64 X2 and Core 2 Duo side by side, so can't comment. However, in that article, the Phenom II X4 is being used. Generally, K10 was faster than Core but behind Nehalem.

Yeah, Phenom II was competitive against Core2, but by that point Nahalem was out and Sandy Bridge was just around the corner.

Really, from the E8600/Q6600 through the i7 920, i7 2600k/i5 2500k, through the 4770k Intel was on a roll. It was really after that Intel went into cruise control, and it cost them long term.

 

[ryao1]

It had more resources but again, lack of IMC means memory latency is abysmal. And still today, bad memory latency means no high performance CPU despite caches are from another world.

Core 2: 32+32 kB L1 + 3 MB L2 (for 2 cores)
Ryzen 9800x3D: 32+48 kB L1 + 2 MB L2 + 8
MB L3 + 24 MB "L4" (L3 and L4 are calculated for 2 cores, just for comparison)

If Core 2 really is "fine" without IMC, Zen 5 also shouldn't need any kind of fast DRAM access. What AMD then does? Zen 6 will have redesigned IO die to improve DRAM access.

Even Intel engineers admitted that not having IMC is very bad thing. They tried to reduce effect of that by putting more cache but even when comparing against Nehalem thats not very convincing. If AMD just didn't have IMC, then Core 2 would have been "fine" without it. But in practice it was evident that when Core 2 runs out of cache, AMD is just better choice. And those situations happen often outside benchmarks.


DDR5 is dual channel just because channel is only 33 bit instead 64. To be more precise, dual channel should be 128 bit memory bus. But if talking without numbers, it's accepted that 128 bit memory channel equals dual channel. Therefore single DDR5 module is still single channel and I will keep talking that way. It's just how original "definition" was and I stick with it.

It's same thing with effective clock speeds. Quad pumping 100 MHz bus "is" 400 MHz effective but when making clock speed adjustments, it's 100 MHz not 400 MHz. Safer to talk absolute values.

They cut the channels in half with DDR5 and gave each module two of them. It makes it annoying since nobody knows what anyone else means when they talk about channels since they don’t know if people are talking about the actual channels or what they would have been had JEDEC kept things the DDR4 way.

The DDR5 channels are 40-bit channels, not 33-bit. The DDR4 channels were 72-bit channels. There is an extra 8-bits in the channel that is not used for data.

To make matters even more confusing, the DDR5 registered DIMMs seem to use the DDR4 channel arrangement.