Custom data center reaches 64 gigatransfers per second through optical PCIe 6.0

Daniel Sims

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Forward-looking: When the group that manages the PCIe specification finalized PCIe 6.0 in 2022, they suggested that data centers would be the earliest adopters of the technology. That roadmap is beginning to play out as a new demonstration of optical connections shows how PCIe 6.0 can increase cluster sizes.

A custom data center from Nubis Communications and Alphawave Semi showcased a PCIe 6.0 connection that hit the specification theoretical bandwidth of 64 gigatransfers per second last month. The performance doubles the data rate of PCIe 5.0, which recently began appearing in the latest consumer PCs.

The Tektronix booth hosted an Alphawave PCIe subsystem with PiCORE Controller IP and PipeCORE PHY that transmitted and received data at unprecedented speeds through a Nubis XT 1600 linear optical engine last week at DesignCon 2024. The test used an optical link, which the demonstrators claim maintains the same bandwidth as copper cables at significantly greater distances.

The Nubis engine supports 16 PCIe 6.0 lanes or Ethernet optical connections at 100Gb/s per lane. The increased bandwidth might allow the two companies to build increasingly large AI and machine learning servers utilizing multiple nodes. Interested parties can sample the XT 1600 by contacting Nubis through the company's website.

When PCI-SIG issued the final PCIe 6.0 specifications two years ago, they said the next generation connections would emerge first in the enterprise, industrial, automotive, military, and aerospace sectors as consumers gradually gain access to PCIe 5.0 components for memory and storage. So far, everything is going as planned. Consumer PCs won't see the PCIe 6.0 spec for several more years.

The consortium is now working on a PCIe 7.0 specification. An early draft emerged about eight months ago, promising to double the data rate again to 128 GT/s, enabling 512 GB/s of bidirectional x16 throughput. In addition to AI and machine learning, initial applications might include 800G Ethernet, cloud computing, quantum computing, hyperscale data centers, and high-performance computing.

Alphawave and Teledyne LeCroy demonstrated correlation methodology for PCIe 7.0 at DesignCon using the former's DSP-based Serializer-Deserializer and the latter's WaveMaster 8650HD 65 GHz, 12-bit high-definition oscilloscope. The demonstration tested the upcoming specification for transmitter jitter, pulse response, and signal-to-noise-and-distortion ratio.

The consortium expects to publish the final PCIe 7.0 specifications in 2025. Hardware supporting PCIe 7.0 could emerge in 2027 or 2028. There's no telling when consumer PCs might gain access to it.

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PCIe is my favorite connection standard. It's backwards compatible til the OG PCIe connections. It's divisible down from x16 to x1. The naming convention makes perfect sense and you can figure out exactly how much bandwidth you have by the lanes and generation. Even better, you can use the lanes for ANYTHING. USB, SATA, NVME, Ethernet, graphics cards, AI accelerators, expansion cards, WiFi adapters...
You can even use PCIe over USB!
The USB-IF needs to learn from their naming convention.
 
I'm more interested in improvements to PCIe 5. Currently, it is costly to add to consumer motherboards for limited (consumer) use cases and is power-hungry. We need to improve the cost-benefit and power usage before we need another 2X in bandwidth.
 
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