TSMC could have 2nm process ready for mass production by 2024

[Shawn Knight]

The big picture: The number of transistors on an integrated circuit have roughly doubled every two years or so since the early 1970s as observed by Moore's law. Eventually (and probably not too much longer from now), Moore's law will end as it'll simply be impossible to shrink the hardware down any further.

Taiwan Semiconductor Manufacturing Company, or TSMC for short, has made a major breakthrough in the development of its 2nm manufacturing process.

As GizChina recounts, TSMC established a research and development team last year to identify a development path for 2nm. Supply chain sources claim TSMC has settled on a new multi-bridge channel field effect transistor (MBCFET) architecture that apparently solves the physical limits associated with the use of FinFET current control leakage from process shrinkage.

The publication also reminds us that TSMC previously said its 2nm R&D and production would take place in Baoshan (China) and Hsinchu, which is in Taiwan. The company further noted it is planning to have four ultra-large wafer fabs covering more than 222 acres.

Sources say the company is optimistic that it can reach a risk trial production yield of at least 90 percent by the second half of 2023 ahead of mass production in 2024. It’s unclear if the ongoing pandemic will impact this schedule.

Image credit: anyaivanova, Ascannio

Permalink to story.

https://www.techspot.com/news/87617-tsmc-could-have-2nm-process-ready-mass-production.html

 

[Cubi Dorf]

Taiwan Semiconductor is doing great thing. Intel may be pressure to spin-off manufacturing like AMD did.

 

[SirDigby]

Daaamn! I remember reading a book when I was 9 that said silicon chips would top off at 5nm, I love science.

 

[VitalyT]

First, I heard 7nm was going to be the smallest possible, then it was 5nm, now it is 2nm. This is all marketing BS, to compensate for the lack of innovative imagination.

Hold ya pants on, nanotube processors are coming!

 

[kiwigraeme]

Whatever it is - it's interesting - we need more power/watt - we need ARM etc - we need renewables etc.
By then we should have good enough laptops running on 30% of power needed today.
I know people hate on Chromebooks etc - but pared down O/S with set functions are good enough for lots of purposes . There will be a windows 10lite - M/S has no choice and they need it for phones etc.
When mobile data becomes super cheap - most devices will have access chips built in - including you main pc - even if only backup

 

[Morphine Child]

What, no one will say it? Ok then, I will.

Meanwhile in 2024: Intel is releasing 14nm+++++++++++++++++ Oven Lake CPUs


But on a more serious note: daaaamn, they are going through those nanometers like hot knife through butter!

 

[quadibloc]

What, they're going to produce 2nm chips within the physical territory of the People's Republic of China? Isn't that dangerous? If it is still the case by then that Chinese firms can't purchase equipment with which to go below 14nm, couldn't this provide China a means of obtaining 2nm chips for military use?

 

[quadibloc]

Daaamn! I remember reading a book when I was 9 that said silicon chips would top off at 5nm, I love science.

Ah, but Intel's 10nm is "really" 18nm, and TSMC's 7nm is "really" 20nm. So instead of a physically impossible 2nm feature size, we're dealing with an increase in density that would be equivalent to making old-style integrated circuits with a 2nm feature size - the density increase is instead achieved by other means.

Of course, when I was 9, they had only started making those new-fangled things called "integrated circuits", and they were still too expensive to use in computers, although that would come soon.

 

[tiddyted]

What, they're going to produce 2nm chips within the physical territory of the People's Republic of China? Isn't that dangerous? If it is still the case by then that Chinese firms can't purchase equipment with which to go below 14nm, couldn't this provide China a means of obtaining 2nm chips for military use?

This report is confused. Baoshan is in Hsinchu, and Hsinchu is in Taiwan. Taiwan is not part of China, and has no intention to be part of China, that's why Taiwan is the only east/southeast Asian country that has the majority of the population rooting for Trump in the US presidential election (It's true, look it up) because they believe he'd fxck with China more than Joe Biden.....

 

[Bamda]

That will be just in time for me to upgrade my system to my new AMD Ryzen 9950XT on an AMD 6 motherboard with PCI-E 6/DDR6/USB 5/Thunderbolt 5 and RDNA 6 graphics card (they finally got RT right!).

 

[Bp968]

First, I heard 7nm was going to be the smallest possible, then it was 5nm, now it is 2nm. This is all marketing BS, to compensate for the lack of innovative imagination.

Hold ya pants on, nanotube processors are coming!

Well, 2nm is somewhere between the width of 20 atoms or 4 atoms, depending on the atom in question. Silicon atoms are .2nm in size so it's the size of *10* silicon atoms. I'm no expert but I suspect if that nm actually means anything anymore that we are going to have some difficulty moving below 1nm or .5nm. I mean 10 atoms wide is already mind melting but 5 atoms or 2 atoms? Even if it's possible to make transistors out of the atom itself then .2nm is the limit with silicon as a medium. And since we seem to work by halving or quartering things (28nm, 14nm, 10nm, 7nm, 5nm, 2nm, etc) I'd guess 1.5, 1 or 0.5nm would be the next step.

I would assume TSMC is working on whatever they plan to do post 2nm if they are far enough along to be saying publicly that they intend to have 2nm ready in 2 or 3 years.

 

[Bp968]

Ah, but Intel's 10nm is "really" 18nm, and TSMC's 7nm is "really" 20nm. So instead of a physically impossible 2nm feature size, we're dealing with an increase in density that would be equivalent to making old-style integrated circuits with a 2nm feature size - the density increase is instead achieved by other means.

Of course, when I was 9, they had only started making those new-fangled things called "integrated circuits", and they were still too expensive to use in computers, although that would come soon.

I have a box of counting "valves" and display valves (nixie tubes) I intended to do something with at some point. The counting valves (decatrons) need between 450 and 600v depending on the gas they have in them (some have hydrogen in them and glow purple. Or should. The hydrogen tends to find ways out of the glass over the years. The joy of being a .1nm sized molecule.)

 

[Endymio]

Daaamn! I remember reading a book when I was 9 that said silicon chips would top off at 5nm, I love science.

TSMC's "2nm" node is nowhere near two nanometers in science; the names are pure marketing now. Based on current and previous nodes, the average feature pitch of that node will likely be around 3X that, or 6-7 nm.

Silicon atoms are .2nm in size

A little larger than that. The covalent diameter is 0.22nm -- but pretty much all semiconductor wafers use some form of straining, which stretches the crystalline structure somewhat.

 

[Bp968]

TSMC's "2nm" node is nowhere near two nanometers in science; the names are pure marketing now. Based on current and previous nodes, the average feature pitch of that node will likely be around 3X that, or 6-7 nm.

A little larger than that. The covalent diameter is 0.22nm -- but pretty much all semiconductor wafers use some form of straining, which stretches the crystalline structure somewhat.

Very cool information! Thanks. Do you have any links about the *actual* feature sizes? I was curious about that when I wrote my post about it being unlikely they could shrink smaller simply due to physics. Then after I posted I saw someone else had mentioned it being a marketing buzzword (possibly you). That seems far more probable than 10 atom wide transistors.

 

[Endymio]

@Bp968, this chart is one you may find helpful. The average feature size is essentially the geometric mean of metal pitch and gate pitch. Or based solely on fin size, we get 21nm (the mean of 30, 6, and 52).

Obviously TSMC hasn't released details of their 2- and 3- nm nodes yet, but we can extrapolate based on what they're doing at 7nm.

 

[Bp968]

@Bp968, this chart is one you may find helpful. The average feature size is essentially the geometric mean of metal pitch and gate pitch. Or based solely on fin size, we get 21nm (the mean of 30, 6, and 52).

Obviously TSMC hasn't released details of their 2- and 3- nm nodes yet, but we can extrapolate based on what they're doing at 7nm.

I couldn't help myself and looked up what process my first computer ran on (it was a TRS-80 when I was 6). It was a Z80 cpu on a 6 μm process! Quite the change even with marketing fluff.

Thanks for the link, that should keep me busy for a while.