WD plans to mass-produce 162-layer NAND by the end of the year, over 200 layers by 2024

Tudor Cibean

Posts: 47   +2
In a nutshell: Western Digital plans to start mass-producing 162-layer BiCS6 3D NAND, which is likely to be used in PCIe 5 SSDs by the end of this year. The company is also working on NAND with 200+ layers meant for datacenter storage, PLC, and ways to bond together multiple 3D NAND wafers to increase the number of layers.

Western Digital, together with partner Kioxia, just gave us a look at their roadmap for the next few years of NAND development. The company plans to introduce its 6th generation BiCS soon, which will feature 162 layers in TLC and QLC configurations.

While that might not sound so impressive considering competitors like Micron have had 176-layer NAND for a while now, WD claims they will shrink the memory cell size by using a new material, resulting in smaller die sizes.

The company hopes that this will allow them to build cheaper storage devices that perform just as well. Mass production of BiCS6 3D NAND is scheduled to start in late 2022, with WD planning to use these chips in products ranging from cheap USB drives to PCIe 5.0 SSDs.

WD also talked about their upcoming BiCS+ memory with over 200 layers, which is set to arrive by 2024. It will feature 55 percent more bits per wafer, 60 percent higher transfer speed, and a 15 percent higher write speed compared to BiCS6.

It's worth noting that BiCS+ is meant to be used only in datacenter SSDs, as the company plans to offer a different class of 2xx-layer NAND for consumer storage, dubbed BiCS-Y.

Western Digital additionally shared that they are working on multiple technologies to improve density and capacity, including PLC, and that they're planning to build NAND with 500+ layers within the next decade.

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Posts: 988   +739
I'll just be happy to see cheaper 4TB and 8TB SSD - and eventually 10TB SSD for under $1000.

They have to be coming - WD and competitor 1 and competitor 2 ( Micron and Samsung??)
Plus isn't USA. Japan. Europe trying to ramp up this stuff as well

I think the engineering challenges must be interesting - minimising heat and interference etc let allowing massive bandwidth increases .
Add in 3D APU/CPUs from AMD - some of the SOCs in the future will be super power complete PCs - minus power, data connectors and cooling .
as an aside a SOC that needed no connections would be super - passive cooling - NFC/BT communication and contactless charging ( I suppose we have it in phones already - but as stand alone button SOCs - program them - throw them in your drone - modular upgrade easy )

It has to come to save Ewaste etc - Button contactless SOCs - update car, TV , receiver, robot - some devices have multiple button holders - keep legacy stuff - specific purpose SOCs eg high power communication SOC , AI SOC
People update whole machines - when only one or 2 parts need updating .

To offset that -more programmable chips are coming as well to counter obsolescent
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The problem is no longer speed or size. These are just unreliable, and the more data you put on them the less reliable they are.