You might already know that PCI Express 4.0 is on its way. Back at the PCI-SIG’s (Special Interest Group) DevCon event in June, it was announced that the standard was complete and undergoing review. Now, the specifications for version 1.0 have been finalized and released.
"I'm pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website,” said PCI-SIG president Al Yanes. "We had previously announced in June this year at our annual DevCon event that the Version 0.9 specification was feature complete and undergoing member IP review.”
The biggest change is that PCIe 4.0 doubles 3.0’s transfer rate of 8 GT/s (gigatransfers per second) and 8Gb/s of link bandwidth per lane to 16 GT/s and 16 Gb/s link BW, which gives a total throughput of 64 GB/s per 16-lane slot.
PCI-SIG had stuck to a four-year release cycle for PCIe 1.0, 2.0, and 3.0, but it’s been seven years since PCIe 3.0 was released back in 2010. The group, which is comprised of almost 800 companies including Intel, Nvidia, and AMD, says this is because the current standard provided enough bandwidth before the rise of technologies such as PCIe NVMe storage and 10GbE network speeds.
In addition to reduced system latency, other advantages of PCIe 4.0 include lane margining, I/O virtualization and platform integration, and extended tags for service devices. It also comes with improved Reliability, Availability, Serviceability (RAS) capabilities.
Like previous PCIe versions, PCIe 4.0 will be backward compatible with older PCIe 1.x, 2.x, and 3.x cards, though newer 4.0 cards won’t work in older boards.
Even though the new specifications have just been finalized, PCI-SIG is already turning its eye to PCIe 5.0. It aims to release an early version of these next generation’s specs, which will again double performance, this time to 32 GT/s, in the second-quarter of 2019.
We probably won’t see many PCIe 4.0-based consumer products arrive until around 2020, but PCI-SIG says there have been plenty of companies eager to jump onboard.
"We’ve seen unprecedented early adoption! Prior to publication, we’ve had numerous vendors confirmed with 16GT/s PHYs in silicon and IP vendors already offering 16GT/s controller. Given the interest, we held a pre-publication Compliance Workshop with preliminary FYI Testing Only for PCIe 4.0 architecture that attracted dozens of solutions. We’re continuing to conduct FYI testing in our workshops throughout the remainder of the year," wrote Yanes.