the 4090 was a really a 4080, but then the couldn't gouge on price. I mean that literally. Going on Die size and chip naming, the 4090 has more in common with an 80 series card than a 90 series card. The X102 dies have always been 80 series cards and the X103 dies have been 70 series card. The "4080 12gb" should have been a 4070 with the 4080 16gb being the TI.
In terms of die size and chip naming, the AD102 is virtually the same as the GA102 -- the only difference being a 3% smaller die size in the newer model. Sure, Nvidia used the GA102 in both a 90 and 80 series card, but if one goes back to the TU102, which was only ever used in the 2080 Ti and the Titan RTX, and the GP102 was only used in the 1080 Ti and Titan X/Xp cards -- in other words, the X102 chip hasn't always been an 80 series card at all.
The use of X103 only started with Ampere -- prior to that, Nvidia used X104 for the next tier:
TU104 -- 2080 Super, 2080, 2070 Super
GP104 -- 1080, 1070 Ti, 1070, 1060
If one compares the GA102 used in the 3080 [10GB] to the full die, it's effectively an 80% full chip (68 vs 84 SMs, 5 vs 6 MB L2 cache). An 80% version of the AD102 would be around 114 or so SMs -- given that the 4090 is 128, that would be too close in terms of performance to really separate the 4090 from the 4080.
But something I'd like you to keep in mind is that RDNA uses a chiplet design in a graphics card, it's something that has NEVER been done before. I'm certain we'll see significant performance increases in later generations as they tweak the tech and make improvements. Hopefully their prices will come down as they improve manufacturing techniques.
The use of chiplets isn't strictly about performance, it's more about improving cost-effectiveness for AMD, but by leaving the cache and memory controllers on a larger, cheaper node (SRAM and IO circuitry isn't going to scale down much more now), it leaves scope for AMD to go with increasingly larger GCDs.
The one used in Navi 31 is quite small at just 326 mm2, so there's definitely room to have something larger. However, TSMC's N5 is already expensive and the next nodes are going to be even more so.
Which raises a problem: how does one improve performance
and lower prices? Sticking with N5 for RDNA 4 would be cheaper than using N3, but the die sizes would be notably larger, thus reducing yields and, in turn, forcing the prices to remain high. If one goes for the newer nodes, to improve the GCD density, performance, and yields, then the manufacturing costs are going to remain high.
The way to reduce the latter is by pre-ordering a shed load of wafers from TSMC, but to do this, one needs to have a market that's going to buy all those chips -- something that the likes of Apple and Nvidia have easily, as does AMD does for its CPUs, but just not for its GPUs.