Anatomy of a Graphics Card: Dissecting the Tech Behind PC Parts

neeyik

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My 2080Ti Black is a big, beautiful piece of machinery, while my 2080Ti FTW3 is even moreso. I absolutely love GPU with built in AIO. I think if more people bought GPU with built in AIO, the worries about thermal throttling would decrease.

I’ve never seen either machine exceed 55° even under peak loads for more than 3 hours.
 

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Excellent article again. Being a veteran of the computer hardware industry, I already knew a lot of the info, but the clarity of the writing is superb! And yes, there were a lot of new bits of info for me.

Same story for me. As long as I've been doing the independent systems builder thing, you can imagine that I know just about all of this, although there were a couple things I had forgotten and relearned.

With that being said, I love this particular "Anatomy of series". In-depth reads like this are fascinating. For someone who is new to this industry, these reads are exactly what they need to learn and feel like experts. I'm almost entirely self-taught, and I want the next generation of independent IT kids to learn the way I did, by reading their favorite tech forums.
 
So in our Radeon HD 6870, with 8 Hynix chips in total, the GPU can transfer up to 2 (transfer per tick) x 2 (double data clock) x 1.05 (baseline clock) x 8 (chips) x 32 (width of stream) = 1075.2 Gbits per second or 134.4 MB/s
You mean 134.4 GB/s?

All of the transmit pins are on one side, and the receive pins on the other; they always go in a group of 4, with each set known as a lane.
This is because PCI Express communication is done using differential signalling, so two pins handle instructions/data and the other 2 pins are for grounding.
I had to re-read it a few times as it sounded quite different from what I remember about PCI Express. And then I went to the PCI Express article of Wikipedia to read it again.
It turned out to be not so wrong, but didn't sound correct either.

One lane has a pair of consecutive pins to transmit data (transmit data + and transmit data -), and another pair to receive data (receive data + and receive data -), so 4 active pins. There're plenty of other ground (I.e unused, inactive) pins to separate these pairs from one another to reduce crosstalk.

Almost all graphics cards use 16 lanes (I.e. PCI Express x16) and each one can transfer 8 bits of data, at a monster rate of 8 GHz.
For PCI Express 3.0 x16, each lane can transfer at the rate of 8 GT/s, 1 bit of data each time. So 1GB/s raw transfer rate for 1 lane, and 16GB/s for 16 lanes.
 
You mean 134.4 GB/s?
Oops! I did indeed - thanks for the feedback.

One lane has a pair of consecutive pins to transmit data (transmit data + and transmit data -), and another pair to receive data (receive data + and receive data -), so 4 active pins. There're plenty of other ground (I.e unused, inactive) pins to separate these pairs from one another to reduce crosstalk.
Yes, this is what was mentioned in the article: a single transmit or receive set of pins consists of 2 transmit/receive (required for the differential signalling) and 2 ground pins. So a single 'lane' comprises 2 receive pins, 2 transmit pins, and 4 ground pins. There are exceptions to this and its where the use of sense pins replace one of the 4 ground pins to tell the system whether the installed card is a PCIe x1, x4, x8, or x16 card.

For PCI Express 3.0 x16, each lane can transfer at the rate of 8 GT/s, 1 bit of data each time. So 1GB/s raw transfer rate for 1 lane, and 16GB/s for 16 lanes.
That bandwidth value doesn't account for the encoding used, so the real peak is nearer 15.7 GB/s - that was mentioned in the article just below the line you referred to.
 
Oops! I did indeed - thanks for the feedback.


Yes, this is what was mentioned in the article: a single transmit or receive set of pins consists of 2 transmit/receive (required for the differential signalling) and 2 ground pins. So a single 'lane' comprises 2 receive pins, 2 transmit pins, and 4 ground pins. There are exceptions to this and its where the use of sense pins replace one of the 4 ground pins to tell the system whether the installed card is a PCIe x1, x4, x8, or x16 card.
Well, "they always go in a group of 4", and then "so two pins handle instructions/data and the other 2 pins are for grounding". The mention of ground pins makes it sounds more like 4 pins consist of 2 pins for signal and 2 ones for grounding, as that signal pins go in pairs is not mentioned.
What you write in the comment makes perfect sense, but the part in the article sounds just weird.

That bandwidth value doesn't account for the encoding used, so the real peak is nearer 15.7 GB/s - that was mentioned in the article just below the line you referred to.
I mean this:
each one can transfer 8 bits of data, at a monster rate of 8 GHz.
It should be 1 instead of 8. And the transfer rate unit should be GT/s, not GHz.
 
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Well, "they always go in a group of 4", and then "so two pins handle instructions/data and the other 2 pins are for grounding". The mention of ground pins makes it sounds more like 4 pins consist of 2 pins for signal and 2 ones for grounding, as that signal pins go in pairs is not mentioned.
What you write in the comment makes perfect sense, but the part in the article sounds just weird.
Thank you for the feedback again - I initially though the article was clear on this, but your comments confirm that this isn't the case. I'll go back and adjust the text so it's better (hopefully).

It should be 1 instead of 8. And the transfer rate unit should be GT/s, not GHz.
Well, my original statement in the article is all kinds of messed up anyway - I forgot my basic electronics knowledge entirely! A binary electronics a single pin can transfer 1 bit of data; since PCI Express uses differential signalling, two pins are required to transfer 1 bit of data. This means a single lane can transfer 1 bit send and 1 bit receive, so a PCI Express x16 card will have 16 lanes transmitting 16 bits in one direction, and 16 bits in the other direction.

The voltage strobes used to time the data latches are, as mentioned, a differential pair, and the latch points are determined on the rise of one strobe, and the fall of the other. So two data latch points are possible per clock cycle and as the clock speeds of the strobes in PCI Express 3.0 is 4 GHz, that gives a data latch frequency of 8 GHz.

I know the industry prefers the term 'transfer rate' and uses GT/s, instead of GHz, but they're the same thing - the former is how many transfers occur per second, the latter refers to a number of events taking place per second. When one talks about the refresh rate of a monitor, we use Hz and yet when we talk about the output of a GPU, we use fps, despite the fact that both systems are handling the same thing: a single frame.

Anyway, a PCI Express 3.0 x16 interface has a theoretical peak bandwidth of:

4 GHz x 2 latch points x 16 lanes x 1 bit per direction = 128 Gbits per second = 16 GB/s

The use of 128b/130b encoding reduces this to:

(128/130) x 16 = 15.754 GB/s in one direction (31.51 duplex).

I'll adjust the article later today, after work, to clarify and correct it.
 
Great writing. I remember saving up and buying my first enthusiast graphics card when I was 17 and collecting my Asus ATI Radeon X800 XT from my local computer shop. I cycled there and had to ring my mum and ask her to collect me in the car because it came in an enormous box that I couldn’t get back on my bike! It had all sorts in there, multitudes of cables, a disc library of free software including driver the game and even a free plasticky webcam! The surprises didn’t end there, after installing the card I noticed that there was a blue glow coming from case, I opened it up and it was LED lights on the card! First time I’d seen that. The card itself was an enormous upgrade on my existing GeForce FX5200! The first game I played on it would have been counter strike :).

This card was a single slot card and it felt enormous at the time, it was just prior to double slot cards becoming the norm, around the same time PCI Express came in to replace AGP.
 
The pinout for the PCIe slot on the GPU is wrong or is unlear which notch you are referring to. Needs to be flipped if you are talking about the notch on the right hand side (looking down at the GPU).

Great aticle nonetheless!
 
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