DDR6 development begins as Samsung, SK Hynix, and Micron target 2028-2029 launch

midian182

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Forward-looking: We're in the middle of a memory crisis that has pushed component prices to unprecedented levels. The outlook is grim, with many predicting the situation will last years. But major memory makers have already started early development of DDR6, with commercialization of the next-gen modules set for 2028 or 2029.

According to Korean publication The Elec, Samsung, SK Hynix, and Micron have asked substrate manufacturers to move forward with DDR6 production. The companies are now coordinating designs and conducting preliminary development of the new memory standard.

The report adds that having received shared designs, manufacturers begun developing substrates that take into account memory thickness, stack-up structure, and wiring. They are currently building initial prototypes and conducting verification.

The Joint Electron Device Engineering Council (JEDEC) drafted the DDR6 standard in late 2024. It has not yet been finalized, so some key specifications, including the number of I/O ports, thickness, and signal standards, are yet to be determined. The current development stage focuses on coordinating detailed specifications based on the designs proposed by each stakeholder, according to The Elec.

Previous reports suggested that DDR6 is set to bring major architectural improvements over DDR5, with baseline speeds beginning at 8,800 MT/s and rising to 17,600 MT/s – double the official ceiling of current DDR5. Overclocked modules are expected to push these speeds even higher, eventually reaching 21,000 MT/s.

Another major DDR6 enhancement is its multi-channel architecture, which uses four 24-bit sub-channels. Compared with DDR5's dual 32-bit layout, this approach improves parallel processing, data flow, and bandwidth efficiency, though it also increases the demands on module I/O design and signal integrity.

Memory makers are also positioning CAMM2 as an important form factor for DDR6, particularly in laptops and other compact systems. The newer module design is expected to deliver better performance, greater capacity, and improved efficiency than traditional DIMMs and SO-DIMMs.

The big question is how much DDR6 will cost by the time it reaches buyers. The current memory crunch has already pushed DDR5 and LPDDR prices sharply higher, driven largely by AI server demand and manufacturers shifting capacity toward higher-margin products.

DDR6 will almost certainly debut in servers and data centers first, where customers are more willing to absorb early-adopter premiums. Consumer modules are unlikely to appear before late 2028 at the earliest, with 2029 looking like a more realistic window for wider availability.

Even then, DDR6 is unlikely to be cheap. Early kits should carry a steep price hike over DDR5, especially if substrate supply remains tight and manufacturers continue prioritizing AI-related memory products, which is almost certain – unless the bubble has popped. Ultimately, it could be some time before DDR6 pricing reaches levels that make sense for mainstream gaming PCs and laptops.

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Expect 2030 or even later for consumers. Price is going to be insane and early DDR6 might be worse than good DDR5 due to bad timings etc. This was the case when we got DDR5 too. Took years before DDR5 made any sense.
 
Expect 2030 or even later for consumers. Price is going to be insane and early DDR6 might be worse than good DDR5 due to bad timings etc. This was the case when we got DDR5 too. Took years before DDR5 made any sense.
The new generation of ram being worse than the highly developed EOL generation has always been the case.
 
I've been excited about all past DDR standards. This one, though, may fall flat on its face ... the move from 32-bit to 24-bit channels is very odd one, almost intentionally designed to cause alignment problems for 64-bit processors.
 
I've been excited about all past DDR standards. This one, though, may fall flat on its face ... the move from 32-bit to 24-bit channels is very odd one, almost intentionally designed to cause alignment problems for 64-bit processors.

My guess is that 4x24=96 allows for higher throughput than 3x32=96, so they're doing that rather than just adding the extra 32bit channel, even though the end result is the same. Though I couldn't tell you why, even if my assumption is right.
 
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