First look: Intel's next leap in data center design starts not with a GPU or accelerator card, but with a single CPU running nearly 300 efficiency cores. The company this week introduced its Xeon 6+ line, codenamed Clearwater Forest, built on the Intel 18A process, Intel's most advanced fabrication technology yet and the first in the 1.8-nanometer class.
The new chips mark a turning point for Intel's strategy in cloud and telecommunications workloads, where efficiency and integration are now prioritized over sheer clock speed.
Clearwater Forest is based on Intel's all-new Darkmont core microarchitecture. Each processor packs up to 288 of these cores across 12 compute tiles, an unprecedented density for a server-grade CPU. Each compute tile holds 24 Darkmont cores, fabricated using the 18A node, and connects through Intel's 3D stacking technology Foveros Direct.
Two separate input/output tiles, built on Intel 7, handle memory, PCIe, and network interfaces, while three base tiles fabricated on Intel 3 anchor the entire structure. Communication between tiles runs through Intel's EMIB (Embedded Multi-Die Interconnect Bridge) links, the same packaging innovation driving the company's high-end GPUs.
That complex assembly is designed in large part to keep data as close as possible to the cores while keeping power draw to a minimum. In Clearwater Forest, the caches were completely re-engineered to suit that goal.
Four Darkmont cores share a 4 MB L2 cache, while the chip's last-level cache surpasses a gigabyte – about 1,152 MB in total – giving hundreds of cores rapid access to frequently used data without depending heavily on external memory bandwidth.
Darkmont itself represents a major step forward for Intel's efficiency-core design. The cores feature an expanded instruction cache of 64 KB, a wider fetch-and-decode path, and a deeper out-of-order execution engine that can track more simultaneous operations. Adding more execution ports boosts both scalar and vector performance.
Although the Xeon 6+ family is built for efficiency, it's equipped with accelerators increasingly vital to data center operators. Each chip includes support for Intel Advanced Matrix Extensions (AMX), QuickAssist Technology (QAT) for cryptographic and compression workloads, and vRAN Boost – a hardware block tailored for virtualized radio access networks.
These integrated accelerators target workloads that would normally require separate AI or networking cards, particularly in edge and telecom deployments running 5G Advanced and upcoming 6G systems. Intel's argument is that by embedding these capabilities directly into the CPU, operators can avoid redesigning their server racks and still scale AI inference and network processing efficiently.
The platform remains compatible with the existing Xeon socket, easing deployment for system builders. It brings 12 channels of DDR5 memory running up to 8,000 MT/s and up to 96 PCIe 5.0 lanes, with 64 of them supporting Compute Express Link (CXL) 2.0 for coherent memory or device expansion. Dual-socket configurations double the available computing resources to 576 Darkmont cores in a single server.
Clearwater Forest reflects a broader shift within Intel's data center roadmap – away from monolithic designs toward disaggregated packaging and from brute performance toward workload specialization through integrated acceleration. For cloud and telecom operators, where every watt and rack unit matters, that emphasis on efficiency is less a design philosophy than an operational requirement.
Intel expects systems featuring Xeon 6+ processors to ship later this year.
Intel's 18A node debuts in the data center with the 288-core Xeon 6+
