Requested readings

Was reading the Samsung EUV article and found myself wondering:

3 nm! ? I remember some science papers published a while back on quantum tunneling at 5 nm? This Wiki Link talks about 1-3nm.

"...Tunnelling occurs with barriers of thickness around 1–3 nm and smaller,[18] but is the cause of some important macroscopic physical phenomena. For instance, tunnelling is a source of current leakage in very-large-scale integration (VLSI) electronics and results in the substantial power drain and heating effects that plague high-speed and mobile technology; it is considered the lower limit on how small computer chips can be made.[19] Tunnelling is a fundamental technique used to program the floating gates of flash memory, which is one of the most significant inventions that have shaped consumer electronics in the last two decades. ..."

T.O.M.A. here because I don't remotely have the physics background reading on this. I'm wonder if dual layer grounded faraday shielding is required on these chips to stop random magnetics (especially including 5G) affecting the circuit walls and thus the data?

If so, would this faraday shielding require true ground circuitry in the system and the wall sockets. I remember some advertising on "The Brick" decades ago concerning lightning backscatter through house grounds that could blow out computer systems unless the grounding line was blocked. Can't remember if it was chokes, FET, or what. So the question would concern whether enough voltage change from external RF in the circuitry occurs to cause effects in a 3nm circuit and will it be affected or ameliorated by one or two levels of copper (faraday shield) and how 'grounded' does that copper have to be. If it does then this 'lower limit' ciircuitry level may be limited to custom designed and built server farms.

Anyone know any readings on this?
 

neeyik

TS Evangelist
Staff member
You're talking about two unrelated phenomena - quantum tunneling and electromagnetic interference. To understand what chip manufacturers are doing to counter the problems caused by the former, have a read of these articles:


In the case of the latter, shielding will only go so far, which is why ECC cache is now commonplace in CPU design, as well as the use of differential signalling.
 

In the case of the latter, shielding will only go so far, which is why ECC cache is now commonplace in CPU design, as well as the use of differential signalling.
Thank you very much. Read both articles with particular usefulness in the Electrical Engineering article. That generated some further reading requirements and I'm chasing them now. e.g.

There is research underway to minimize tunneling by electrons through thin materials. One such approach is a spin lattice, which can localize or “contain” the stray electrons. Spin transfer torque (STT) MRAM changes the spin of electrons using electrical current rather than magnetism.

volume inversion You turn it on and the center of the wire will invert before the edges.

Mocuta points to transistor body scaling, which is gradually becoming a requirement for maintaining electrostatic control. Quantum effects show up as thinner fins, which ultimately will force a move to gate-all-around transistor structures using nanowires or nanosheets

the semiconductor band structure gets ‘quantized,’ so instead of a continuous energy spectrum for the carriers, for example, only discrete energy levels are allowed,


For some reason (attempting to retain face by not saying stupdity) I had 5G in my thoughts as terahertz nanometer wavelengths instead of gigahertz millimeter wavelengths and the thought those would generate electromagnetic surface effects in the circuitry wires in sub-5 micron transistors adding to electron tunnelling effects.

It was a stupid question (hence TOMA) but your answer pointed me to more specialized readings. Thank you again.