SiFive RISC-V cores and Microchip processors will power NASA's future space missions

Alfonso Maruccia

Posts: 88   +41
Staff
Why it matters: The X280 is a new RISC-V CPU being developed to survive the harsh conditions of outer space and let NASA scientists accomplish their next missions. Expectations are high: at least a 100x increase in computing power, while keeping the same energy consumption.

NASA will soon perform a significant upgrade to the systems employed in its spaceflight computers, adopting the RISC-V architecture developed and provided under open-source licenses. NASA selected SiFive to provide the CPU cores, a fitting choice as the company headquartered in San Mateo, California was founded 7 years ago to develop RISC-V based hardware (where "V" indicates this is the fifth generation RISC instruction set) and put compatible processors on the market.

SiFive is a fabless chip company, so actual production of the chips will be in the hands of Microchip Technology, a company based in Chandler, Arizona specialized in manufacturing microcontrollers, EEPROM chips, and other IC products.

NASA awarded a $50 million contract to the two companies, expecting the final delivery of the new X280 CPU in a 3-year timeframe. X280 will be the computational foundation of the High Performance Spaceflight Computing (HPSC) project, NASA's initiative to design and develop new spaceflight technology capable of providing "at least" 100 times the computational capability of currently employed systems, while using the same amount of energy.

X280 will replace the RAD750 processor, an aging PowerPC-based CPU manufactured by BAE Systems and employed in several NASA missions since 2005. The Mars Perseverance rover and the recently launched James Webb telescope are two of the most celebrated space endeavours made possible by the RAD750 CPU.

The X280 CPU currently in development for the HPSC system will utilize 8 SiFive Intelligence RISC-V vector cores with 4 additional cores, which will provide the computational capability jump NASA is projecting before retiring today's space computers. According to SiFive, the massive increase in performance will help usher in new possibilities for autonomous rovers, vision processing, space flight, guidance systems, communication, and other mission elements in space exploration.

Another paramount feature of the X280 will be its tolerance to radiation: HPSC will be specially designed to survive the harsh and hostile space environment, controlling many space activities with no possible aid from Earth and ensuring its ability to operate and provide reliable results for most critical operations.

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defaultluser

Posts: 510   +389
Other than probes and big telescopes, there's hardly any market here; only a company as desperate s sifive would bother!

we will see if planetary rovers continue to use the already serviceable PowerPC/MIPS, of if these become universal?
 

hwertz

Posts: 198   +117
TBH, I'm not seeing desperation here.

MIPS Inc. themselves have decided to o with RISC-V based designed rather than further develop their own MIPS CPUs -- which are used quite a bit in wireless access points etc. It's very similar in concept to the MIPS instruction set, just if it was designed 20-30 years later so the problematic design aspects of MIPS are avoided (like MIPS' jump instruction that can only jump +/- 128MB... which I'm sure was ample in 1985 but causes compiler a fun time for larger software now). It's actually a pretty nice modern CPU design, quite a small instruction set but they picked the instructions a modern compiler would like to have to build highly performant code.

Linux has been ported to RISC-V for a while and it has compiler support for quite a while; the embedded OSes like vxworks are regularly ported to new hardware and in fact vxworks for instance has supported RISC-V for several years.

Don't get me wrong, if the existing MIPS and PowerPC hardened CPUs remain available, they should feel free to continue to use them (after all once it's in space it's not like you have to worry about parts availability...) But I see having a RISC-V available as a positive.
 

defaultluser

Posts: 510   +389
TBH, I'm not seeing desperation here.

MIPS Inc. themselves have decided to o with RISC-V based designed rather than further develop their own MIPS CPUs -- which are used quite a bit in wireless access points etc. It's very similar in concept to the MIPS instruction set, just if it was designed 20-30 years later so the problematic design aspects of MIPS are avoided (like MIPS' jump instruction that can only jump +/- 128MB... which I'm sure was ample in 1985 but causes compiler a fun time for larger software now). It's actually a pretty nice modern CPU design, quite a small instruction set but they picked the instructions a modern compiler would like to have to build highly performant code.

Linux has been ported to RISC-V for a while and it has compiler support for quite a while; the embedded OSes like vxworks are regularly ported to new hardware and in fact vxworks for instance has supported RISC-V for several years.

Don't get me wrong, if the existing MIPS and PowerPC hardened CPUs remain available, they should feel free to continue to use them (after all once it's in space it's not like you have to worry about parts availability...) But I see having a RISC-V available as a positive.

its just repeating the same task, just with a brand-new architecture (with no existing Linux software stack for embedded devs)

yeah, you pay no licensing fee, but you still have to pay to harden the cores(same engineering fee the rad750 pays). in the end, your only gain seems to be adding more cores for free ( ricv interconnect is at-least respectable). but you still have the privilege of reinventing (if closed-source), or porting (if open, and actually maintained) the rest of your MIPS/PowerPC software stack!

theirs a lot of risk inherent with that complete tool rewrite (especially for a kernel that wiill need to be proven mathematically stable on this new arch)

 
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kinetix

Posts: 56   +46
This will take time.
Maybe they can make the design fast, thanks to SiFive and RISC-V.
but the validation....
...that will take years.
 
> like MIPS' jump instruction that can only jump +/- 128MB... which I'm sure was ample in 1985 but causes compiler a fun time for larger software now

I hate to break this to you, but RISC-V's JAL instruction only goes ±1 MB, which is less than MIPS.

It's no big deal because a pair of instructions (AUIPC;JALR) can do a ±2 GB relative jump/call, which is indeed more than MIPS. The compiler always outputs this pair, and the linker reduces ("relaxes") it to a single ±1 MB JAL whenever possible, which is most of the time.

ARM64 like MIPS can do ±128 MB with a BL instruction, but needs three instructions for ±2 GB range: ADRP;ADD {immed};BLR

>Linux has been ported to RISC-V for a while and it has compiler support for quite a while; the embedded OSes like vxworks are regularly ported to new hardware and in fact vxworks for instance has supported RISC-V for several years.

Right. RISC-V is a simple RISC ISA. comparable to many other RISC ISAs. It's very simple to support in GCC and with only simple instructions it's hard to introduce code-generation or optimisation bugs. RISC-V GCC is as reliable as GCC itself.

The seL4 kernel has been verified on RISC-V.
 

DZillaXx

Posts: 539   +692
IIRC the RAD750 is pretty much a powerpc G3 from back in the day. And is still being used today... A Chip from the 90s.

A new modern platform was going to be massively faster, regardless if it was Risc-V or X86.