Forward-looking: Building NAND with ferroelectric transistors can dramatically cut power consumption by sidestepping a core limitation of conventional NAND, according to a new study from the Samsung Advanced Institute of Technology. The company says it has finally cracked long-standing issues with capacity scaling and memory windows that undermined earlier attempts.
As the AI boom fuels massive data-center buildouts, demand for memory keeps climbing – and with it, the notoriously high power consumption of today's NAND. Samsung's researchers are pitching a new architecture that could sharply reduce those energy costs. Mobile devices might also benefit if the findings catch on.
Traditionally, NAND scales by stacking layers on top of each other. The catch is that fully tapping the memory's capacity means pushing power through those layers in sequence. That pass voltage increases with every layer added, sending total power draw up with it.
Previous attempts to limit power draw have resulted in reduced memory windows. Even other proposals based on ferroelectrics failed to resolve the balance between capacity scaling and power efficiency.
FeFETs eliminate pass voltage entirely which dramatically reduces power consumption. At the same time, they maintain multi-level cell density of up to five bits per cell – on par with, or better than, today's top-end memory.
On top of that, limited threshold-voltage tunability in oxide semiconductors has made them less viable for high-end devices. Samsung's approach pairs those oxide semiconductors with a ferroelectric structure to form ferroelectric field-effect transistors (FeFETs), which sidestep those constraints.
FeFETs eliminate pass voltage entirely and can drop power consumption by up to 96 percent compared to conventional NAND. At the same time, they maintain multi-level cell density of up to five bits per cell – on par with, or better than, today's top-end memory. Samsung proposes scaling FeFET designs by stacking transistors with 25 nm short channels. The findings, produced by more than 30 researchers from Samsung's technology institute and semiconductor R&D center, were recently published in Nature.
AI processors and data centers require so much memory that they've disrupted the NAND industry, with shortages expected to last at least through 2026. Cutting memory power by nearly 100 percent could significantly shrink the overall energy footprint of AI hardware.
Samsung isn't alone here – other companies are also exploring ferroelectric routes to build persistent, non-volatile memory that hangs onto data after power loss. Whether this approach prevails over other contenders remains to be seen, but the implications could be huge for everything from large-scale compute to everyday consumer tech.