Cutting corners: Faced with rising memory costs, Meta says it is reusing old DDR4 RAM in its servers rather than buying new hardware. The company revealed this week that it is repurposing DDR4 memory from decommissioned servers into its new DDR5-only machines, using a custom CXL ASIC that avoids the compatibility issues and major latency penalties that typically come with mixing memory generations. The design reportedly cuts AI inference server count by up to 25% and reduces job-restart and fragmentation overhead by 33%.
Documents presented by Meta at ISCA 2026 this week reveal that its new "MemServers" are powered by AMD's Epyc Turin CPUs, featuring 158 cores and 316 threads.
The Turin chips technically support only DDR5 RAM, but Meta got around that limitation with a custom CXL 2.0 ASIC called "Vistara," designed to let legacy DDR4 DIMMs work seamlessly alongside DDR5 platforms.
Each MemServer packs 1 TB of combined memory, including 768 GB of DDR5-6400 local RAM and 256 GB of DDR4-2400 CXL-attached RAM connected via Vistara. Meta explained that Vistara's software stack treats the DDR4 memory as a "distinct, CPU-less NUMA node," separate from the local DDR5 DRAM nodes attached directly to the processor.
Treating the two sets of DIMMs as separate nodes lets the system keep the most frequently accessed data in faster DDR5 memory while relegating cold pages to the slower DDR4 pool. The approach helps Meta optimize hardware resources and cut memory costs without meaningfully compromising performance.
Meta's team also modified the Linux CXL driver to get the older DIMMs working on platforms that don't officially support them. The company noted that all Linux kernel CXL driver code used for Vistara is either already upstream or on track to be added to the codebase soon.
Meta states that the Vistara ASIC was built to "bridge DDR4 memory to host processors via a CXL 2.0/1.1-compliant PCIe Gen5 x16 interface." Driven by custom RISC-V processors, each Vistara chip integrates two independent 72-bit DDR4 channels, supporting speeds up to 3,200 MT/s and capacities up to 256 GB per chip using 64 GB DIMMs.
Meta is not the only company experimenting with combining DDR4 and DDR5 in the same system.
South Korean fabless semiconductor firm Panmnesia says it has also developed a custom CXL controller and a CXL fabric switch with Port-Based Routing, giving hyperscalers another way to cut hardware spending.
Like Meta, Panmnesia presented its CXL research at ISCA 2026 on June 29. The company said it plans to commercialize its new CXL products soon and is currently sampling its PCIe 6.4/CXL 3.2 Fusion Switch with select customers. Panmnesia is also developing a PCIe 7.0/CXL 4.0 Combo IP controller that adds support for the latest CXL 4.0 features.