What just happened? Nvidia has released more information about its upcoming Vera data center CPU this week, including key details about the custom Olympus cores that are purpose-built for agentic AI workloads. The company also claimed that the new core architecture offers faster single-core performance than competing products.
Part of Nvidia's Vera Rubin platform, the Arm-based Vera CPU is designed to perform complex reasoning, facilitate tool execution, generate code, and plan tasks for AI agents. Developed as a multi-purpose chip, it can also handle scientific data processing and reinforcement learning, which demand more CPU power than typical AI workloads.
Each Vera CPU incorporates 88 Olympus cores, 176 physical threads, a 64KB four-way L1 instruction cache, and 164MB of unified L3 cache on a monolithic compute die. It also features a 48-instruction decode queue. The mid-core incorporates a 96KB six-way L1 data cache and a 2MB eight-way L2 cache, alongside a hardware graph prefetcher for data-intensive graph and analytics workloads.
Each custom core comprise a wide front-end with optimized branch predictors, a mid-core with critical path acceleration, and an execution engine with complex vector optimization. They offer high-bandwidth instruction fetch supporting up to 16 instructions per cycle and include a 10-wide decode engine processing up to ten fused instructions per cycle.
Olympus' branch prediction subsystem includes a neural branch predictor capable of reducing wrong-path execution on specific branch patterns. Combined with the wide decode path, it also helps improve front-end throughput for latency-sensitive workloads, such as agentic AI and reinforcement learning.
The Olympus core architecture integrates Nvidia's Spatial Multithreading technology, enabling flexible resource partitioning. It also supports the Scalable Coherency Fabric for 3.4 TB/s of on-die core-to-core bandwidth, 1.2 TB/s of aggregate SOCAMM2 LPDDR5X memory bandwidth, and up to 1.5 TB of memory capacity.
Vera supports 1.8 TB/s connectivity on NVLink-C2C, PCIe 6.4, and CXL 3.1. It supports dual-socket scaling, too, with each socket providing 176 PCIe Gen 6 lanes. To improve latency in dual-socket systems, Vera uses a software-based solution where each socket presents itself as a single NUMA domain, avoiding fragmentation and creating a clean two-NUMA-node topology.
To back up its claims about Vera's performance, Nvidia published its internal SPEC CPU 2026 test results from earlier this month. The data seems to show that Vera delivers up to 1.8 times the performance of AMD's Epyc Turin 9755 systems in select agentic AI workloads, such as 714.cpython_r. However, the results have yet to be independently verified.