DDR SDRAM shoot out: Crucial PC2100 vs. OCZ Performance PC2400

Posted by Toby Crundwell on November 08, 2001
Manufacturers: Crucial Technology / Crucial UK & OCZ Tech

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CAS

CAS = Column Access Strobe. A memory’s CAS rating is generally comprised of 3 different settings; CAS Latency, RAS to CAS delay and Precharge time. All of which are usually linked and referred to simply as CL (CAS Latency). On the OCZ and Crucial modules these settings were always the lower number (although as we'll see they can be overclocked)

CAS Latency: This sets the CAS latency timing of the DRAM system memory access cycle when SDRAM system memory is installed. Setting this to 2 will yield better performance, although may be less stable if your SDRAM is not CAS2 rated. 2.5 is slower & should be used when DDR SDRAM isn't CAS2 rated or you want to improve stability.

RAS to CAS delay: This sets the delay between the CAS & RAS strobe signals. Basically setting this to a low number will improve performance, setting this to a higher number can improve stability (Particularly when running the memory above rated speed).

Precharge delay: Much like the above 2 settings, setting this to a low number will improve performance & setting this to a higher number can improve stability (Particularly when running the memory above rated speed).

Installation

As was expected, there was nothing adverse about installing the two DIMMs. Both ran faultlessly at a speed of 133Mhz.

Test machine:

• AMD Athlon Thunderbird 100Mhz FSB @ 850+Mhz

• Asus A7A 266, FSB @ 100+Mhz

• Memory running at clock + 33Mhz

• OCZ Titan 2 Ultra SE

SiSoft Sandra 2001te standard’s memory benchmark was used to compare the two modules.

We see fairly predictable results, with the Crucial coming within only 2Mhz of the OCZ, and with both willing to run on decreased latencies. In fact, the Crucial could load up windows at much higher frequencies, but Windows reported registry errors at these breakneck speeds.

Select General Impressions CAS, Installation and Maximum Speed Achieved Availability and Conclusion

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