In brief: An agentic AI system has reportedly designed a complete RISC-V CPU core from scratch in just 12 hours, marking the first time an autonomous agent has built a working CPU from specification to GDSII. Like human engineers, the AI agent followed the conventional design cycle – design, build, test, and refine – but did so entirely on its own rather than relying on separate automation tools for each stage.
The processor – dubbed VerCore – was created by chip design startup Verkor.io using its agentic AI system, Design Conductor. According to a whitepaper published by the company, VerCore features a five-stage pipeline design with an in-order, single-issue architecture and a 1.48GHz clock speed.
The chip reportedly scored 3,261 on the CoreMark benchmark, a specialized tool used to measure the performance of microcontrollers and CPUs in embedded systems. The modest score suggests that VerCore can barely keep pace with an entry-level Intel Celeron SU2300 from mid-2011, indicating that the new design is unlikely to compete with modern CPUs.
It is worth noting that Design Conductor is not itself an AI model, but a harness tool that constrains large language models to follow a specific set of instructions in pursuit of a defined objective. In this case, it worked autonomously with a 219-word specification document provided by the VerCore engineers and produced a GDSII file that can be used to fabricate an actual CPU core using EDA software.
A major caveat worth noting is that VerCore has not yet been physically fabricated; it has only been validated in simulation using the reference RISC-V ISA simulator, Spike. Its layout was designed using ASAP7 PDK, an open-source academic design kit that models a 7nm-class process node. The predictive PDK was developed by engineers at Arizona State University in collaboration with ARM Research and is available on GitHub under the BSD 3-Clause license.
Verkor plans to release all relevant design files by the end of this month, allowing hardware designers and third-party engineers to verify the company's claims. The company also plans to showcase an FPGA implementation of VerCore at the Design Automation Conference in Long Beach, California, in July.
This is not the first time AI has been used for digital hardware synthesis. In 2020, a fine-tuned GPT-2 model dubbed DAVE was trained on Verilog code to generate simple hardware logic circuits. This was followed in 2023 by an 8-bit processor layout reportedly designed entirely by GPT-4. As of 2026, most leading large language models are capable of designing and testing chips with basic functionality, albeit with varying levels of reliability.