Japanese chip company plans 2nm prototype production by 2025

Daniel Sims

Posts: 824   +33
Staff
In brief: Japanese and US companies have partnered to manufacture 2nm semiconductors within the next few years. With help from Japan's leadership, they hope to compete with Taiwanese industry leader TSMC. One company's president recently revealed the roadmap for 2nm chips.

This week, Atsuyoshi Koike, president of Japanese chip venture Rapidus, told Nikkei Asia that the company plans to establish a prototype production line for 2nm semiconductors by the first half of 2025. If successful, the roadmap would put the company right behind industry titan Taiwan Semiconductor Manufacturing (TSMC) which also wants to enter 2nm mass production in 2025.

Rapidus and IBM announced a partnership in December to further develop and manufacture a 2nm semiconductor design that IBM first unveiled in 2021. The process promises a 45 percent performance boost over 7nm nodes by packing over 50 billion transistors onto a fingernail-sized chip. It can also provide the same performance as 7nm while using 75 percent less energy. The US tech giant doesn't manufacture chips in-house. Instead, it licenses its designs out to partners.

Koike said the Japanese company's long-term goal is for 2nm mass production sometime in the late 2020s. The effort is part of a cooperation between Japanese and American private companies with partial funding from the Japanese government's Ministry of Economy, Trade, and Industry.

Previous reports said the groups want to establish the first Japanese 2nm facilities between the fiscal year 2025 and 2027. The initial wave of semiconductors would likely go toward quantum computers, data centers, flagship smartphones, and possibly military applications.

Flagship smartphones are also the main focus for TSMC's N3 3nm node, which went into full production just before the end of last year. The company's primary client for the early N3 application is Apple, which will use the chips for the iPhone 15 it plans to launch later this year.

Meanwhile, Intel wants to debut its 20 Ångström (20A) – essentially a rebranded 2nm – in 2024 to catch up with TSMC. The first clients for the upcoming node will be Amazon and Snapdragon chipmaker Qualcomm.

Samsung, the number-two player behind TSMC, started manufacturing 3nm chips in June and has an improved design planned for 2024. Like its Taiwanese rival, the company wants to begin 2nm mass production in 2025. In October, Samsung revealed a roadmap with plans to reach 1.4nm by 2027.

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Kashim

Posts: 224   +318
We'll see how this pans out. I do hope they succeed, because more competition in this sector is always nice. However, I would not hold my breath as far as projected timelines are concerned. I have a feeling these announced dates will get pushed back.
 

Axeia

Posts: 77   +77
We'll see how this pans out. I do hope they succeed, because more competition in this sector is always nice. However, I would not hold my breath as far as projected timelines are concerned. I have a feeling these announced dates will get pushed back.
It is likely, IBM has however been working on this stuff for ages so perhaps it's possible. Given Intel's recent history is pretty much guaranteed they won't make their own deadline.
So my money is on this new venture beating Intel to the market. At least for mass production, I wouldn't be surprised if Intel launches a single model of some laptop CPU that's only sold in a single region in limited numbers. They've done that trick before to meet deadlines on paper.
 

Endymio

Posts: 2,009   +2,116
The [2nm] process promises a 45 percent performance boost over 7nm nodes...
Anyone who thinks Moore's Law isn't dead should consider these figures. Taking the node names at face value, 2nm is 3.5 nodes ahead of 7nm, meaning it should offer more than 11x the transistor density. In reality, it will have 2.5x the density and only a measly 45% performance boost.

The node names are pure marketing fiction at this point, yes. But the problems are deeper than that. Moore's Law was always predicated on density improvement causing per-transistor costs to decay exponentially. However N3 will be the first node in history where a majority of configurations have a per-transistor cost flat or higher than the prior node. If N2 is the same, that'll effectively break the entire consumer electronics upgrade cycle.