JEDEC releases next-gen DDR5 memory specification

nanoguy

Posts: 521   +7
Staff member
Something to look forward to: As CPU core counts continue their upward trend, there's been a pressing need to improve DRAM bandwidth as well. DDR5 SDRAM will quadruple capacity per die and double the effective bandwidth, all while lowering power consumption thanks to architecture refinements.

The JEDEC Solid State Technology Association has announced the final DDR5 memory specification with a series of significant upgrades over the previous standard that is now over six years old and in dire need of a worthy replacement. After all, the standards body took two years more than originally planned to align what's coming next to the growing needs of system manufacturers.

Must read: Anatomy of RAM

The DDR5 SDRAM standard quadruples the density of DDR4, going from 16 Gb per die to 64 Gb. This will allow manufacturers to make DIMMs with capacities going all the way up to 2 TB. In terms of maximum data rate, DDR5 will offer 6.4 Gbps, or double the data rate of DDR4. However, the first modules to hit the consumer market will only be capable of reaching 4.8 Gbps, which is still a significant improvement over the 3.2 Gbps maximum of DDR4.

The power requirements have been lowered as well. The standard operating voltage is 1.1 V on DDR5 versus 1.2 V needed for DDR4. And while that may seem rather small, there are several architectural improvements that will simplify motherboard designs, while retaining the same 288 pin count.

DDR5 SDRAM modules won't be compatible with current DDR4 slots. Individual DIMMs will have to come with an integrated voltage regulator -- JEDEC calls this the "pay as you go" philosophy where manufacturers will only need to purchase as many voltage regulators as the number of DIMMs that are installed in the end systems. It's not entirely clear at this point, but this could also improve yields as well as power consumption, particularly for data center applications.

Interestingly, every DDR5 DIMM will work in dual-channel mode by itself, as the memory banks are now addressable on two independent 32-bit sub-channels (40-bit for ECC memory), which is a similar design to GDDR6 and LPDDR4 memory.

Furthermore, the burst length for each of those channels has been increased from 8 bytes (BL8) to 16 bytes (BL16), meaning DDR5 SDRAM will be able to perform two 64 byte operations in the same amount of time it takes for DDR4 SDRAM to perform a single one.

The earliest we can expect to get our hands on platforms with DDR5 support is Q4 2021-Q1 2022. Companies like Micron and SK Hynix are already sampling DDR5 with industry partners and mass manufacturing of DDR5 memory is expected to start later this year.

Permalink to story.

 

Vulcanproject

Posts: 1,160   +1,923
"every DDR5 DIMM will work in dual-channel mode by itself"

Very significant. Single DIMM machines will get an easy bandwidth boost from that. No doubt the SO-DIMM spec that will follow will make a big difference for notebook manufacturers who usually cut corners by having a single module at the expense of dual channel bandwidth.
 

texasrattler

Posts: 919   +398
"every DDR5 DIMM will work in dual-channel mode by itself"

Very significant. Single DIMM machines will get an easy bandwidth boost from that. No doubt the SO-DIMM spec that will follow will make a big difference for notebook manufacturers who usually cut corners by having a single module at the expense of dual channel bandwidth.
Desktops also do this in pre builts/OEMs. Seen this from HP in their Omen series and from iBuypower PC.
 

neeyik

Posts: 1,118   +1,102
Staff member
"every DDR5 DIMM will work in dual-channel mode by itself"

Very significant. Single DIMM machines will get an easy bandwidth boost from that. No doubt the SO-DIMM spec that will follow will make a big difference for notebook manufacturers who usually cut corners by having a single module at the expense of dual channel bandwidth.
There isn't an increase in bandwidth as it's going from 1 x 64 bits to 2 x 32 bits, so peak throughput will remain the same. However, it just means that this total bandwidth can be used more effectively - it's the same reason why graphics cards have multiple memory controllers, rather than just one or two. The higher bandwidth that DDR5 offers comes from higher bus speeds.
 

Lounds

Posts: 488   +369
There isn't an increase in bandwidth as it's going from 1 x 64 bits to 2 x 32 bits, so peak throughput will remain the same. However, it just means that this total bandwidth can be used more effectively - it's the same reason why graphics cards have multiple memory controllers, rather than just one or two. The higher bandwidth that DDR5 offers comes from higher bus speeds.
From first glance it looks like DDR5 could offer double the bandwidth throughput, this is massive, the jump from DDR3 to 4 wasn't that big, infact people who had triple channel i7 setups from X58 motherboards had better performance for a few years of DDR4 before we got higher speed modules. As people have mentioned this will benefit OEM's the most as a lot of laptops and desktops are shipped with 1 Dimm of memory. As for the average Joe it means that DDR5 will now rival the higher end desktops that support quad channel DDR4 in terms of bandwidth and capacity.
 

neeyik

Posts: 1,118   +1,102
Staff member
I mispoke before. The dual sub-channels, by themselves, don't improve the peak bandwidth. However, the increased burst length, bus speeds, and dual channels altogether raise the effective bandwidth.

For example, DDR4-3200 (the highest rating in the JEDEC spec) has memory chips running at 400 MHz, with the I/O at 4 times that (1600 MHz) and since data transfers are double again, this leads to 3200 MT/s.

DDR5 will still have chips running at that same kind of speed speed (there are significant engineer challenges to getting DRAM to run faster), but the I/O speeds are double again. The sub-channels are narrower but as they have burst lengths that are double that of DDR4, the combination of all 3 changes (channels, burst length, speeds) means that DDR5 transfers twice as much data per data operation than DDR4 does.

You're right that this will benefit laptops, or anything using integrated graphics, although the biggest benefit is just the use of the sub-channels (a la GDDR6), as this will increase the efficiency of the memory system, and perhaps more so that just running at ever higher bus speeds.
 

HardReset

Posts: 781   +327
This whole dual channel confusion is easy avoid this way:

- Single DIMM module is 64-bit, no matter if it's DDR5 or something else

- Dual channel memory is essentially same as "128 bit memory bus"

= dual channel memory still requires at least two memory modules
 

pit1209

Posts: 119   +166
"Interestingly, every DDR5 DIMM will work in dual-channel mode by itself, as the memory banks are now addressable on two independent 32-bit sub-channels (40-bit for ECC memory), which is a similar design to GDDR6 and LPDDR4 memory."

Does this mean that there is not going to be any benefits using two DIMMS anymore?
 

HardReset

Posts: 781   +327
"Interestingly, every DDR5 DIMM will work in dual-channel mode by itself, as the memory banks are now addressable on two independent 32-bit sub-channels (40-bit for ECC memory), which is a similar design to GDDR6 and LPDDR4 memory."

Does this mean that there is not going to be any benefits using two DIMMS anymore?
Two messages above:

This whole dual channel confusion is easy avoid this way:

- Single DIMM module is 64-bit, no matter if it's DDR5 or something else

- Dual channel memory is essentially same as "128 bit memory bus"

= dual channel memory still requires at least two memory modules
 

Squid Surprise

Posts: 3,221   +2,106
It's already stated and on the roadmap they delayed the new socket specifically for this.
3rd/4th quarter, 2021 Zen 4 - AM5, DDR5, PCIe5, Infinity Fabric 3.0, Thunderbolt 3 support, USB4.
Lisa Su stated it was on track before the release of 2022.
I hope that's true :)
 

quadibloc

Posts: 180   +104
Wow, if in ECC mode there's an extra 8 bits for each 32 bits of memory, then each 64 bits will come with 16 bits of error correction, enough to allow for DECTED instead of SECDED correction - double error correction, triple error detection. And presumably enough for chipkill instead as well.
 

SixTymes

Posts: 36   +17
Talk about slow to the table...DDR5 was suppose to be final and out to consumers 3 years ago. JEDEC sure milk releases.