TL;DR: Japan is intensifying its campaign to rejoin the top tier of the semiconductor industry, and Hokkaido has emerged as the center of that push. The island – better known for dairy farms, ski resorts, and summer flower fields – is now home to one of the world's most ambitious chip-building efforts: Rapidus, a government-backed foundry venture aiming to produce 2-nanometer logic chips at scale.
The political and financial stakes are unusually high. Tokyo has committed roughly $12 billion to Rapidus so far, on top of tens of billions of dollars in broader semiconductor subsidies, with additional support from domestic heavyweights including Toyota, SoftBank, and Sony.
The new fab complex – known as IIM-1, for Innovative Integration for Manufacturing – is rising in Chitose, close to New Chitose Airport and within commuting distance of Sapporo, inside the Bibi World industrial park. Planners selected the site for its reliable water and power infrastructure as well as its relatively low seismic risk compared with other candidate locations in Japan – a nontrivial consideration for vibration-sensitive lithography tools.
The plant's design reflects both industrial and regional priorities. Rapidus chief executive Atsuyoshi Koike says the fab will feature a grass-covered exterior to visually blend with Hokkaido's surrounding fields. Behind that green shell, the complex is being configured as a tightly integrated front- and back-end manufacturing base, with an initial 2 nm pilot line scheduled to ramp ahead of full mass production, which the company targets for 2027.
Technically, Rapidus is trying to enter the market at one of the most demanding points on the process-node roadmap. Earlier this year, the company announced that it had successfully fabricated 2 nm-class gate-all-around (GAA) transistors as prototypes, a milestone enabled by its partnership with IBM and access to IBM's nanosheet process IP.
Only TSMC and Samsung have demonstrated comparable capabilities at this geometry, while Intel is pursuing its own trajectory by moving directly from a 7 nm-class process to roughly 1.8 nm rather than stopping at 2 nm.
For Japan, demonstrating working 2 nm devices on 300 mm wafers is essential – not because it immediately closes the competitive gap, but because it signals that domestic engineers can execute GAA integration at the leading edge.
Rapidus has installed a state-of-the-art EUV scanner from ASML at IIM-1, making it the first company in Japan to deploy this class of tool for advanced logic manufacturing. The system – part of ASML's high-volume production line – can process hundreds of wafers per hour at full production doses and incorporates high-power light sources, precision optics, and ultra-fast wafer stages.
Bringing the tool online required unusually tight coordination. Rapidus had to align construction, cleanroom preparation, and tool delivery on a compressed schedule, meeting stringent temperature, humidity, and contamination specifications necessary for EUV operation.
Inside the fab, Rapidus is adopting a process architecture that diverges from typical high-volume manufacturing. The company plans to run all front-end steps on single-wafer tools rather than the hybrid batch/single-wafer approach used at most mature fabs. In this model, each wafer undergoes deposition, etch, cleaning, and related steps individually, enabling engineers to adjust parameters in real time and collect high-resolution data at every layer.
This data-centric flow is designed to lower defect densities and accelerate yield learning – critical at 2nm, where even minute variations in line width, overlay, or sidewall profiles can render devices unusable. Rapidus argues that faster detection of drift and anomalies will shorten cycle times from tape-out to qualified production and support one of the company's selling points: faster turnaround and more customized manufacturing, rather than competing head-to-head with larger foundries on volume.
Rapidus is also building a packaging ecosystem in parallel. At a nearby Seiko Epson facility in Chitose, the company is setting up a back-end pilot line, known as RCS, to develop redistribution-layer interposers, chiplet-based integration, and 3D packaging. These techniques are slated to migrate into a back-end line at IIM-1 starting in 2027, creating a unified manufacturing chain from transistor formation through advanced packaging and test – with a "known good die" regime to improve assembly yields.
Even with massive political momentum, skeptics see large structural gaps. The ASEAN+3 Macroeconomic Research Office estimates that Rapidus's current funding still falls well short of the roughly ¥5 trillion – about $31.8 billion – required to reach stable, full-scale 2nm production. Analysts at the Center for Strategic and International Studies likewise point out that Rapidus has no track record in advanced manufacturing and must rely largely on IBM's limited technology transfer rather than the deep, iterative process knowledge that TSMC and Samsung have accumulated over decades.
The result is a transformation project whose success is far from assured. Rapidus must bring a first-of-its-kind fab online, complete the transfer of complex process recipes from overseas R&D sites, drive defect densities low enough for commercial yields at 2nm, attract committed customers, and prove that its single-wafer, AI-heavy production model can meaningfully shorten cycle times.
If it delivers on even most of those fronts, Japan will re-establish a meaningful foothold at the leading edge of semiconductor fabrication. If it stumbles, IIM-1 may instead become a case study in the formidable difficulty of re-entering the top tier after ceding it to more experienced rivals.
Image credit: BBC