In context: After an extremely difficult 2018 that featured both, ongoing delays in producing new 10 nm chips and the unceremonious exit of its CEO, Intel is also facing the toughest competitive environment it’s seen in some time. Not only is a resurgent AMD becoming a serious threat in both the PC and server markets, but Nvidia has managed to snag most of the focus in the attention-grabbing AI market, and new offerings from Qualcomm show that its computing capabilities are much stronger than many may have realized.
Competition really is a great thing, and if you ever really needed a reminder of how and why, look no further than the recently rejuvenated, albeit humbled, semiconductor behemoth based in Santa Clara, CA.
As a result of all these challenges, Intel has been forced to rethink a number of its previous investments, reorganize its increasingly scattered divisions, and put together a strategy that could both directly address the new competitive environment and leverage many of the unique capabilities that make Intel what it still is today (lest we forget): the largest semiconductor company in the world.
Thankfully, the company recently laid out its new vision through a series of announcements about new technology directions and strategy delivered at an industry analyst summit and tech press event. Specifically, on the technology side, the company discussed a new variation on the “chiplet” concept that leverages a new 3D chip-stacking technology codenamed Foveros. Instead of trying to continue along the traditional Moore’s Law path of increasing transistor density horizontally via large and complicated monolithic chips created on a single process technology node, Foveros technology represents an important pivot towards vertical density.
Practically speaking, what this means is that the company can combine several different chips created at different process sizes, while still increasing overall transistor density, in a single chip package. It’s a fascinating development that highlights how Intel is still able to maintain its long history of manufacturing advances, despite the challenges it faced in bringing 10 nm chips to market.
The first real-world example of Foveros’ ability to integrate heterogenous pieces together is the newly announced Sunny Cove architecture, expected to ship in 2019, which will combine both 10 nm Core “big” CPUs with several “little” Atom CPUs, into a new hybrid x86 architecture (which, yes, sounds conceptually very similar to the “big.Little” architecture designs that Arm and its customers have been talking about for years). The idea is to enable much more power-friendly x86 designs—it will be interesting to see what kinds of devices this new platform will enable.
The first real-world example of Foveros’ ability to integrate heterogenous pieces together is the newly announced Sunny Cove architecture, expected to ship in 2019, which will combine both 10 nm Core “big” CPUs with several “little” Atom CPUs, into a new hybrid x86 architecture
At the strategic level, the company highlighted a new approach built on six pillars—Process, Architecture, Memory, Interconnect, Security and Software—that manages to tie together a number of different resources that Intel owns into a nicely unified, and powerful, vision of the future of computing. The process advances are built not just on Foveros, but the simultaneous work its been doing for both 7nm and 5nm, both of which are expected to benefit from the hard-won lessons the company learned on 10nm. Throw in the announcements about plans for new fabs and it’s clear the company is focused on moving forward aggressively on the process front.
Architecturally, the company discussed both the wide range of different architectures it’s creating, including CPU (scalar), GPU (vector), AI (matrix) and FPGA (spatial), compute offerings, as well as advancements in each of those areas. Over the years, Intel has amassed an impressive collection of different companies and architectures, but this was the first time it provided a unified vision that tied all the pieces together. The event also saw the first release of a few more details on their upcoming dedicated GPU effort, currently codenamed Xe and scheduled for release in 2020.
On the memory side, the company highlighted its advances in Optane storage and memory products. Intel emphasized new types of memory that break down the barriers between traditional DRAM and storage, and enable the creation of more sophisticated and much faster overall computing system designs. These memory capabilities are a unique and often overlooked advantage Intel offers versus most all of its competition. Given the exploding amounts of data being created and processed, these memory technologies will be critically important for the increasingly large data sets that data center-based components are going to need to have. (The fact that a simpler form of 3D stacking process technology is also used to build many Optane parts certainly doesn’t hurt either.)
The need to provide better and faster connections between various elements is another key capability in building more sophisticated chip and system designs in an increasingly heterogenous computing world. True to form, Intel talked about a wide range of options it offers in this area as well. From 5G modems to silicon photonics to new ultra-high-speed serial connections between chiplet components in stacked 3D designs, Intel has a number of interconnect technologies that it can leverage in future components and devices.
Security, of course, is a key factor for any company today, and, though Intel has faced some big concerns around Spectre, Meltdown, and other related chip architecture flaws, the company recognizes the need to incorporate security capabilities into all of its offerings. In particular, Intel is investing to integrate a multi-prong security story that reaches across the chip level, SOC level, board level, and software level to ensure the safest possible devices.
Finally, one of the most audacious new goals for Intel is a new software strategy built around what they’re temporarily calling One API. The basic concept is to create a layer of software abstraction that would allow programmers to write at this higher level, then smartly take advantage of whatever hardware system capabilities are available in a given system, from hybrid chip architectures to unique memory offerings and more. In theory, this includes the ability to send certain bits of code to one chip type and other chunks to other types while still maintaining most of the raw performance that would be available if programmers wrote straight to the metal. It’s a goal that many people have talked about—and it still remains to be seen if Intel can execute on it—but it would certainly provide a key advantage to Intel in an increasingly heterogeneous computing world.
In addition to these important technology and strategy announcements, it was clear that there was a new attitude within Intel’s executive ranks. In addition to a humbler approach, the company openly talked about being a smaller player in a bigger market. Clearly, the goal was to re-emphasize the fact that the company is now seeing themselves being able to participate in a broader range of opportunities than it traditionally has. There was even a joking reference about bringing back former CEO Andy Grove’s desire for Intel to always be paranoid about the competition—a quality that, frankly, seemed to fade over the last few years.
At roughly 107,000 employees, Intel is a very large organization, and it can often be tough to turn big ships around. It’s clear, however, that there’s a fresh attitude and approach there that certainly makes them appear to be much better prepared for an increasingly diverse computing future. Now, if they could only fill that CEO job….
Bob O’Donnell is the founder and chief analyst of TECHnalysis Research, LLC a technology consulting and market research firm. You can follow him on Twitter @bobodtech. This article was originally published on Tech.pinions.