AMD details Zen 3 and Zen 4 alongside roadmap for next-gen Epyc Milan and Genoa CPUs

onetheycallEric

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At the HPC-AI Advisory Council UK conference, AMD divulged some details regarding its upcoming Zen 3 and Zen 4 architectures, as well as establishing a timeline for the next-gen Epyc Milan and Genoa processors.

AMD's Zen architecture and Epyc processors have been nothing short of a watershed moment for AMD in the server space, where a mere two short years ago, Intel held ~99% of the market. As things stand now, AMD could be on track to claw away as much as 10% of the lucrative market throughout 2020 and AMD looks to maintain its forward momentum hot off the heels of its Zen 2 Epyc "Rome" CPUs.

AMD set out to update its Zen architecture on a yearly basis, and this latest roadmap reiterates that. Milan is already in tape out, which means the chips are likely being sampled among some of AMD's closest customers. Milan will boast Zen 3 cores on a refreshed 7nm+ node, and should enter volume production in Q3 2020. Milan chips will scale up to 64 cores, the same as current-gen Rome, and drop into the same SP3 socket. Additionally, Milan looks to leverage 2 threads per core, putting to rest the rumor that it could come with as many as 4 threads per core.

Milan will also use the same nine-die configuration as Rome, with eight compute dies and one I/O die. However, it appears AMD will make some alterations under the hood, equipping each CCD (core complex die) with up 32MB of unified L3 cache.

Sitting out further on the horizon is Genoa, which will presumably use Zen 4 cores. Looking at the roadmap, Genoa will also signal the end for the SP3 socket, introducing the SP5 platform. Genoa would also arrive with support for DDR5 memory, and AMD is no doubt mulling a shift to PCIe 5.0. Genoa chips are currently in the "design" phase, and should land sometime in 2021.

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neeyik

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Looks like the L3 cache is going to be fully unified, looking at that diagram. Currently in Zen 2, each core gets 4 MiB of cache, grouped into a 4 core complex (hence the 16 MiB); it would seem that a complex is going to consist of 8 cores, which should help reduce the latency hit when one complex needs to read/write to another complex's cache.
 

quadibloc

Posts: 255   +148
I'm almost surprised to hear that the SM4 rumor about the next generation of Ryzen is not true. After all, not only is it an obvious way to squeeze out more performance from a chip... but, as well, software, thanks to the original Ryzen, has gotten more thread-aware than it used to be, so it would seem like now is the time that such a step would work.
But on reflection, multithreading only provides more throughput if there's empty space on the pipeline.
AMD's old Bulldozer architecture didn't have multithreading at all, but since it had such long pipelines (and hence such a low IPC) it would have been a natural for high multi-way multithreading. Zen, not so much.
 
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Dimitrios

Posts: 727   +565
I'm almost surprised to hear that the SM4 rumor about the next generation of Ryzen is not true. After all, not only is it an obvious way to squeeze out more performance from a chip... but, as well, software, thanks to the original Ryzen, has gotten more thread-aware than it used to be, so it would seem like now is the time that such a step would work.
But on reflection, multithreading only provides more throughput if there's empty space on the pipeline.
AMD's old Bulldozer architecture didn't have multithreading at all, but since it had such long pipelines (and hence such a low IPC) it would have been a natural for high multi-way multithreading. Zen, not so much.
Oddly your comment made me think about INTEL's netburst technology for some reason.
 

Puiu

Posts: 4,303   +3,060
TechSpot Elite
I'm almost surprised to hear that the SM4 rumor about the next generation of Ryzen is not true. After all, not only is it an obvious way to squeeze out more performance from a chip... but, as well, software, thanks to the original Ryzen, has gotten more thread-aware than it used to be, so it would seem like now is the time that such a step would work.
But on reflection, multithreading only provides more throughput if there's empty space on the pipeline.
AMD's old Bulldozer architecture didn't have multithreading at all, but since it had such long pipelines (and hence such a low IPC) it would have been a natural for high multi-way multithreading. Zen, not so much.
They might actually be working on SM4, but I doubt it will be ready in time for Zen3. Where there's smoke, there's usually fire.

We could see this implemented in Zen 4, for the server chips, which is currently still in development. SM4 makes a lot more sense there than on desktop PCs.
 
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Jeffrey2009

Posts: 45   +14
No confirmation on PCIe 5.0 yet, the article only stated AMD may be mulling it over.
Considering Intel's announcement about PCIe 5.0 for their motherboard chipset of the 2nd 10nm generation CPU, AMD is probably follow the trend to deploy the PCIe 5.0 with DDR5 memory on their Zen4 architecture.
 

neeyik

Posts: 1,687   +1,936
Staff member
I'm almost surprised to hear that the SM4 rumor about the next generation of Ryzen is not true. After all, not only is it an obvious way to squeeze out more performance from a chip... but, as well, software, thanks to the original Ryzen, has gotten more thread-aware than it used to be, so it would seem like now is the time that such a step would work.
But on reflection, multithreading only provides more throughput if there's empty space on the pipeline.
AMD's old Bulldozer architecture didn't have multithreading at all, but since it had such long pipelines (and hence such a low IPC) it would have been a natural for high multi-way multithreading. Zen, not so much.
There's only been a few CPUs ever made that support more than 2 way SMT, with the most notable of these being IBM's Power8 processor. This CPU could support up to 8 threads per core; Anandtech tested one against a couple of Intel Xeons:






The rest of the Anandtech makes for interesting reading, as it really hammers home the point that multicore is better than SMT for the majority of applications; 4 way or higher SMT is only effect where the required IPC is low, but cache and parallelism is highly in demand.