I looked at your charts and compared CPUs by subtracting instead of dividing.
That helped explain some of the results.
The R3 uses half of a physical chip (CCX in AMDspeak), the R5 & R7 use one whole CCX (I think the R5 is just an R7 with 1 or 2 defective cores), and the R9’s use 2 CCX’s (again guessing that the 9900 has a defective core somewhere). This matters because of the size of the L3 cache available to each group. The R3 can only use half of the CCX’s L3, the R5/R7 the whole L3, and the R9’s get the second CCX’s L3 cache.
This shows up perfectly in the compile time benchmark; the times depend almost entirely on how much L3 cache is on tap. The L3 is half as fast as both the R5 and the R7, which barely differ from each other. And the R9’s are almost exactly twice as fast as the R5/7 pair.
Some of the other benchmarks show a similar but less extreme cache effect. I think this helps explain why the R5 and the 9900 seem just a little sweeter than their cousins.
Welcome to Techspot bud, I am happy you have joined us. This is a great place to be a part of. You are mostly correct, you are just getting mixed up with CCX and CCD terminology. So I can understand what you meant, and on the whole you do have the right idea, it is just your terminology that needs correction.
An 3300x is actually 1 entire CCX with all 4 cores enabled. And an 3100x is 2xCCX with 2 cores enabled per CCX. And an CCX is located in an CCD with up to 2xCCXs per CCD, so an 3800x and lower CPUs CCXs are located in 1 CCD which is 1 chiplet (regardless of core count) and an 3900x/3950x are comprised of 2xCCDs which consist of 4xCCXs at 2xCCXs per CCD, and each CCD is one chiplet. I think you are getting confused with CCDs and CCXs. And the CCXs communicate with each other over the Infinity Fabric.
An 3700x is also 2x4 cores CCXs with all 4 cores enabled per CCX which together comprise 1xCCD (fully enabled CCD as it were). Ryzen Master shows this clearly, it labels my 3700X as 1x CCD (CCD 0) split into 2x4 core CCXs called CCX 0 and CCX 1. And those 2xCCX (1xCCD) are located in 1 chiplet whereas an 3900x/3950x are 2x4 core CCXs per CCD with 2xCCDs in total (2x chiplets).
So AMDs current layout is 1xCCX is 4 cores when fully enabled, but there are 2xCCXs per chiplet which is actually counted as 1 fully enabled CCD. So my 3700x consists of CCX 0 and CCX 1 and those two combined equal 1xCCD, in this case CCD 0. And an 3900x/3950x will have 2xCCD (CCD 0 and CCD 1) comprised of 2xCCXs per CCD (CCX core count depending on CPU model).
So an 3300x is half of one fully enabled CCD, but an entire 1xCCX. But it is still an CCD nonetheless, just not a fully enabled CCD, as it only has 1x CCX that is actually enabled and not 2x4 core CCX enabled CPU like my 3700x.
And an 3950x is the fully enabled 2xCCD (2x chiplets) with each CCD comprising of 2x4 core CCXs. And all CPU have an IO die chiplet as well. So an fully enabled 3950x comprises 2xCCDs chiplets consisting of 2x4 core CCXs per CCD and 1x IO chiplet.
Does that make sense? Or must I try be more specific for you? I tried to make it as uncomplicated as I could, my apologies if it is a bit disjointed and a bit of a mess, I do tend to do that sometimes. So once again, my apologies if it comes across that way, that was not my intention.
Here is an article explaining the difference if I am not making any sense (which wouldn't surprise me, I am not great at explaining sometimes).
AMD’s Ryzen CPUs are made up of core complexes called CCDs and/or CCXs. But what is a CCX and how is it different from a CCD in an AMD processor? Let’s have a look. There are many factors responsible for AMD’s recent success in the consumer market. But, the chiplet or MCM design (Multi-chip...
www.hardwaretimes.com
And each Ryzen 3000 (desktop CPU) has 16mb L3 cache per 1xCCX, and 32mb when both CCXs are present (such as 3600/3700x/3800x etc). And 64mb for 3900x/3950x.
So you are correct an 3300x (and 3100x) does only have access to 16mb L3 cache. It is only CCD/CCX that your are getting mixed up with, everything else seems sound. But the fact that the 3300x does not suffer from latency penalties that the other 2xCCX CPUs (or 4xCCX CPUs) suffer from with cross-CCX penalties when fetching data from another CCXs cache, or passing threads from 1 CCXs core/s to another CCX cores, that actually helps it make up quite a bit of ground compared to CPUs featuring 2xCCXs or more.
But the added cores (and cache) of the R5/R7/R9 will usually win out at the end of the day in core heavy (and some other) situations, despite any penalties. They just don't scale as well as Intels monolithic die, but AMD is correcting this somewhat with Ryzen 4000 (Zen3) CPUs and their 8 core CCXs.
But like I said, on the whole you are correct and I understood exactly what you meant and where you are coming from, it is just terminology at the end of the day. But you do have the right idea, and I can see you do understand on the whole. You just need AMDs terminology and you are perfect.
Anyway, once again welcome to Techspot bud, I am glad you have joined us.