Looking ahead: The 2026 launches of Venice and MI400 are expected to represent one of AMD's most significant product shifts since the debut of Epyc Rome and MI100. Both initiatives are central to AMD's strategy of delivering end-to-end solutions for cloud computing, AI, and high-performance computing infrastructure.
AMD's data center roadmap became clearer this week as the company confirmed plans to launch its next-generation Epyc Venice processors and Instinct MI400 accelerators in 2026. The upcoming lineup represents a major technological leap for the chipmaker, reinforcing its momentum in high-performance computing and AI infrastructure.
Epyc Venice CPUs will be based on AMD's new Zen 6 architecture and manufactured using TSMC's 2-nanometer process node. This marks AMD's first adoption of the advanced node, promising substantial improvements in performance per watt.
According to the company, prototypes of the Venice silicon are already running in AMD's labs, demonstrating strong gains in compute density and memory throughput compared with current generations.
Each Venice processor will scale up to 256 cores and 512 threads – a notable increase even over AMD's dense Epyc Bergamo platform – while optimizing interconnects and cache hierarchies for higher throughput. The company projects a 70 percent or greater uplift in overall performance, alongside expanded memory bandwidth, targeting workloads ranging from cloud-scale computing to technical simulations.
Lisa Su, AMD chair and CEO, told investors during the third-quarter earnings call that development of the next-generation Epyc Venice platform remains on schedule. She noted that AMD's 2-nanometer silicon is already demonstrating strong performance and efficiency in the lab, with major cloud providers beginning early platform testing ahead of launch.
Su described customer demand and industry engagement with Venice as the strongest AMD has seen to date, adding: "We remain on track to launch our next-generation 2-nanometer Venice processors in 2026."
Alongside Venice, AMD will debut the Instinct MI400 AI accelerator family, introducing a redesigned compute engine built for next-generation AI workloads. The MI400 series will incorporate 432GB of high-bandwidth memory and deliver up to 19.6TB/s of memory bandwidth, positioning it for large-scale model training and inference. The accelerators also feature improved interconnect architecture and integrated networking to boost scalability and power efficiency across clustered deployments.
AMD's upcoming Helios platform, a rack-scale AI computing framework, will also integrate MI400 accelerators, unifying AMD's chip, software, and system design efforts for large-scale training environments. Su described the data center AI business as entering "its next phase of growth," highlighting accelerating momentum from customers and ecosystem partners in preparation for 2026 availability.
The dual introduction of Venice CPUs and MI400 accelerators underscores AMD's intent to expand its footprint in enterprise and hyperscale computing. While details such as final configuration options and pricing remain under wraps, the company's roadmap reflects an aggressive approach to competing with Intel and Nvidia in both CPU and GPU markets, as semiconductor manufacturing moves into the 2-nanometer era.