RAM overclocker breaks the 9,000 MT/s barrier with AM5's new firmware update

Jimmy2x

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Why it matters: AMD's relationship with its AGESA microcode and the DDR5 memory standard has been rocky since the platform's launch in September of last year. From SOC voltage issues to instability above specific frequencies, problems with the platform have prevented users from pushing the limits of DDR5's capabilities.

Earlier this week, several AM5 motherboard manufacturers began rolling out AMD's latest AGESA update (1007B). According to reports from AM5 users and overclockers that received the update, the new firmware substantially increases AM5's overall DDR5 compatibility and support.

Before the update, 6000 to 6200 MT/s was considered the upper limit of AMD's DDR5 stability range. A tweet from Buildzoid outlined how the new update allowed the well-known tech guru and overclocker to reach speeds of 8,000 MT/s on a mid-tier AM5 motherboard.

Another notable PC overclocker, Chihhua "HiCookie" Ke, managed to push his DDR5 even further thanks to the update, reaching a speed of 9,058MT/s on a set of Gigabyte's new Aorus DDR5-8400 memory. The minimal voltage required to sustain both the rated speed and the overclock is even more impressive.

Frequently higher speeds, tighter timings, and pushing beyond the limits of a memory module's rating can require substantial voltage increases. HiCookie managed to maintain the 9,000+ MT/s speeds on only 1.4v.

"This is absolutely bonkers," the overclocker said in a Facebook post proving the feat. "DDR5-9000 Just 1.4V on B650E Tachyon!"

HiCookie's overclock was achieved using a new Aorus Tachyon B650 motherboard, designed explicitly for overclocking enthusiasts. The board features two DIMM slots, advanced power delivery, enhanced memory layout and signaling support, and other overclocking-specific features designed to push the limits of the AM5 platform. HiCookie paired the board and RAM with a Ryzen 7 7800X3D processor for his overclocking attempts.

The 9,000 MT/s mark is a substantial milestone for the AM5 platform, as is the increase in supported RAM frequency and fabric clock stability. The overclocking successes from Buildzoid, HiCookie, and others occurred within a few days of the new code's release. With positive results like the new AGESA code and DDR5 support stacking up in AM5's win category, AMD may be on the cusp of turning yet another corner and quickly closing in on more of Intel's enthusiast-grade market share.

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I have seen the 1.0.0.7.a update for my board last week but not tested it yet. I'll wait to find out if there is a .b revision. I run at 6400 and it's on a knife edge. If a new update lets me reduce voltage I'll be impressed. There has been a lot of criticism with various problems on the platform. I was confident though these memory issues were always a case of AM5 needing to mature a little and have the rough edges tidied up.
 
Doesn't AM5 show that there aren't gaming performance increases with memory speeds above 6000 with Ryzen 7000 series processors don't scale? Maybe this is in preparation for Ryzen 8000 bios updates?
 
I'm hearing this setting is useless since it's not 1:1:1 when exceeding 6400.
And the Zen 4 3d cpus will likely have no significant delta gains, while the zen4 non 3d cached cpus might benefit with some tweaking.
Also not sure if it was mentioned but this is still in beta.
 
I tried 1.0.0.7a, but it doesn't help my Geil ddr5 to reach its EXPO 5600 rating. It's still stuck at 4800.
 
Zen4 has the quirk of having one 32 bit data path for each CCD.
This means that with an IF at 2000mhz , we get a bandwidth of 64GB/s.
But with the memory at 6000MT/s, we already have 96GB/s.
That means when data has to pass to the CPU, it can only do it at the limit of the Infinity Fabric.

So CPUs like the 7600/7700/7800X3D, will be always limited by the Infinity Fabric.
Only dual CCD Zen4 CPUs, like the 7900X and 7950X will have enough IF bandwidth not to limit the memory bandwidth.
 
Zen4 has the quirk of having one 32 bit data path for each CCD.
Bytes, not bits. The data paths between the CCDs and the IOD in Zen 4 desktop SKUs are 16 bytes per clock cycle read and 32 bytes per clock cycle write.

SoC_31.png


The IF-to-UMC is 32 bytes bi-directional. So that's 32 GB/s of read bandwidth per CCD, and 64 GB/s for write, and the same for the IF-to-UMC.

The maximum speed for non-overclocked memory is DDR5-5200, which gives 41.6 GB/s per DIMM pair (83.2 GB/s if both channels are used), so it's already more than the IF.
 
Bytes, not bits. The data paths between the CCDs and the IOD in Zen 4 desktop SKUs are 16 bytes per clock cycle read and 32 bytes per clock cycle write.

SoC_31.png


The IF-to-UMC is 32 bytes bi-directional. So that's 32 GB/s of read bandwidth per CCD, and 64 GB/s for write, and the same for the IF-to-UMC.

The maximum speed for non-overclocked memory is DDR5-5200, which gives 41.6 GB/s per DIMM pair (83.2 GB/s if both channels are used), so it's already more than the IF.

You have the read and write values mixed up.
It's 32 bits for read. And 16bits for write.
 
Oops! Moar coffee is needed!

Happens to the best of us.

Also consider that those slides from AMD don't tell the whole story.
Although it states the write speed is only 16bits, when we test for bandwidth, the writes always end up much faster.
 
Bytes :)

An analysis done by Chips and Cheese, using a Ryzen 9 7950X, two DIMMs of DDR5-6000, and FLCK set to 2 GHz, does show that DRAM write bandwidth is lower than read:

zen4_bw_access_patterns.png


Read performance is typically more important than write, anyway/

Yes, bytes. Seems like I need another coffee as well. 😄

I know about ChipsAndCheese. Really great site for in-depth tech analysis.
But their results on write bandwidth seems different from other memory tests. For example, AIDA64 always shows much greater write bandwidth.
For example, if you run the memory AIDA64 memory test, on a 7600X, the reads will be around 60GB/s. But writes will be around 90GB/s.
Maybe this could be something Techspot might want to do an article on.

Regardless. My point was that on a single CCD ZEN4 CPU, overclocking the memory is pointless as there is no gains to be had in memory bandwidth. Better to focus on lowering latency.
 
Well I did the update and that worked better than expected.

6400 CL32
IF @ 2133.

Not a problem. Sk Hynix modules rated to 1.4v though. I think the voltage is probably overkill now. I think you could lower latency or voltage stably. More testing required.
 
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