Packaging articles

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TSMC unveils plans for giant AI chips to meet surging compute demands

The big picture: The semiconductor industry is approaching a significant milestone as TSMC prepares to expand the physical scale of its chip packaging technology. At its recent North American Technology Symposium, the company detailed plans for a new generation of CoWoS (Chip-on-Wafer-on-Substrate) technology, enabling the assembly of multi-chiplet processors much larger than those currently in production.